KR850000784A - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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Publication number
KR850000784A
KR850000784A KR1019840003098A KR840003098A KR850000784A KR 850000784 A KR850000784 A KR 850000784A KR 1019840003098 A KR1019840003098 A KR 1019840003098A KR 840003098 A KR840003098 A KR 840003098A KR 850000784 A KR850000784 A KR 850000784A
Authority
KR
South Korea
Prior art keywords
semiconductor element
lead frame
lead
semiconductor device
manufacturing
Prior art date
Application number
KR1019840003098A
Other languages
Korean (ko)
Other versions
KR890002136B1 (en
Inventor
히로시 야마다
Original Assignee
아라끼 쯔네오
칸사이닛뽕 덴기 가부시기 가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 아라끼 쯔네오, 칸사이닛뽕 덴기 가부시기 가이샤 filed Critical 아라끼 쯔네오
Publication of KR850000784A publication Critical patent/KR850000784A/en
Application granted granted Critical
Publication of KR890002136B1 publication Critical patent/KR890002136B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음.No content.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 반도체장치의 횡단면도.1 is a cross-sectional view of a conventional semiconductor device.

제2도는 제1도의 요부 측단면도.2 is a side cross-sectional view of the main part of FIG.

제3도는 리이드프레임에의 반도체소자의 마운트상태를 표시한 평면도.3 is a plan view showing the mounting state of the semiconductor element on the lead frame.

Claims (1)

리이드프레임의 방열판에 반도체소자를 고정하는 동시에, 반도체 소자의 전극과 리이드를 금속세선으로 접속하는 공정과, 이 리이드 프레임을 수지모울드 장치에 반도체소자를 포함한 주요부분이 캐비리부에 위치하도록 세트함과 동시에, 금형을 압착하는 공정과, 수지모울드장치의 캐비티부에 수지재를 주입하는 공정을 포함하여, 상기 금형 압착시에, 리이드프레임의 리이드 및/또는 수지모울드 장치의 분리면에 형성된 경사부 혹은 돌기에 의하여, 리이드의 일단을 방열판의 상면으로부터 강제적으로 이간시키는 것을 특징으로 하는 반도체장치의 제조방법.Fixing the semiconductor element to the heat sink of the lead frame, and connecting the electrode and the lead of the semiconductor element with a fine metal wire, and setting the lead frame so that the main part including the semiconductor element in the resin mold device is located in the cavity part. At the same time, the step of pressing the mold and the step of injecting a resin material into the cavity portion of the resin mold apparatus, wherein the inclined portion formed on the separated surface of the lead frame and / or the resin mold apparatus at the time of the mold pressing Or by protruding one end of the lead from the upper surface of the heat sink forcibly. ※참고사항:최초출원 내용에 의하여 공개하는 것임.※ Note: This is to be disclosed based on the first application.
KR1019840003098A 1983-06-29 1984-06-04 Semiconductor devices of making method KR890002136B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58119958A JPS6010632A (en) 1983-06-29 1983-06-29 Manufacture of semiconductor device
JP58-119958 1983-06-29

Publications (2)

Publication Number Publication Date
KR850000784A true KR850000784A (en) 1985-03-09
KR890002136B1 KR890002136B1 (en) 1989-06-20

Family

ID=14774412

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840003098A KR890002136B1 (en) 1983-06-29 1984-06-04 Semiconductor devices of making method

Country Status (2)

Country Link
JP (1) JPS6010632A (en)
KR (1) KR890002136B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1247649B (en) * 1990-10-31 1994-12-28 Sgs Thomson Microelectronics RESIN ENCAPSULATION PROCEDURE OF A POWER SEMICONDUCTOR DEVICE MOUNTED ON A HEAT SINK REMOVING THE WIRES FROM THE HEAT SINK THROUGH THE ACTION OF THE COUNTER-MOLD WHEN THE MOLD IS CLOSED

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS554913A (en) * 1978-06-26 1980-01-14 Hitachi Ltd Resin molding method

Also Published As

Publication number Publication date
KR890002136B1 (en) 1989-06-20
JPS6010632A (en) 1985-01-19

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Payment date: 19950615

Year of fee payment: 7

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