JPS55103771A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55103771A
JPS55103771A JP1015979A JP1015979A JPS55103771A JP S55103771 A JPS55103771 A JP S55103771A JP 1015979 A JP1015979 A JP 1015979A JP 1015979 A JP1015979 A JP 1015979A JP S55103771 A JPS55103771 A JP S55103771A
Authority
JP
Japan
Prior art keywords
elements
regions
distance
region
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1015979A
Other languages
Japanese (ja)
Other versions
JPS6253954B2 (en
Inventor
Kenji Oka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1015979A priority Critical patent/JPS55103771A/en
Publication of JPS55103771A publication Critical patent/JPS55103771A/en
Publication of JPS6253954B2 publication Critical patent/JPS6253954B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To form two elements equivalently by a method wherein a quadrilateral region, with each of its vertices less than 180°, is divided into 4 regions by its diagonals, an element is provided in each region, elements in regions not adjacent to each other are electrically connected in parallel.
CONSTITUTION: In the J-FET, a square region, with all of its vertices being 90°, are divided into four regions, an element is formed in each of the resulting triangles, and two elements in regions not adjacent to each other are electrically connected. This J-FET is formed in the direction inclined by an angle θ" with respect to the inclination of the epitaxial layer. The distance between the two elements, x0, multiplied by √2/2 becomes the maximum for the channel distance x. But since x0 is the distance between the two elements, it becomes very samll, so that the channel thicknesses of the two elements become almost the same for the deviation of the epitaxial layer in any direction.
COPYRIGHT: (C)1980,JPO&Japio
JP1015979A 1979-01-31 1979-01-31 Semiconductor device Granted JPS55103771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1015979A JPS55103771A (en) 1979-01-31 1979-01-31 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1015979A JPS55103771A (en) 1979-01-31 1979-01-31 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS55103771A true JPS55103771A (en) 1980-08-08
JPS6253954B2 JPS6253954B2 (en) 1987-11-12

Family

ID=11742493

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1015979A Granted JPS55103771A (en) 1979-01-31 1979-01-31 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55103771A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214398A (en) * 2006-02-10 2007-08-23 Nec Corp Semiconductor integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4943878U (en) * 1972-07-20 1974-04-17

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4943878U (en) * 1972-07-20 1974-04-17

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007214398A (en) * 2006-02-10 2007-08-23 Nec Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
JPS6253954B2 (en) 1987-11-12

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