JPS56153765A - High-voltage withstanding semiconductor device - Google Patents

High-voltage withstanding semiconductor device

Info

Publication number
JPS56153765A
JPS56153765A JP5694380A JP5694380A JPS56153765A JP S56153765 A JPS56153765 A JP S56153765A JP 5694380 A JP5694380 A JP 5694380A JP 5694380 A JP5694380 A JP 5694380A JP S56153765 A JPS56153765 A JP S56153765A
Authority
JP
Japan
Prior art keywords
diffused
diffused layer
layer
junction
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5694380A
Other languages
Japanese (ja)
Inventor
Chiharu Tsunoishi
Takashi Suga
Hiroyuki Ono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shindengen Electric Manufacturing Co Ltd
Original Assignee
Shindengen Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shindengen Electric Manufacturing Co Ltd filed Critical Shindengen Electric Manufacturing Co Ltd
Priority to JP5694380A priority Critical patent/JPS56153765A/en
Publication of JPS56153765A publication Critical patent/JPS56153765A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To miniaturize a chip by forming a plurality of small diffused regions which are independetly aligned in lines around a diffused layer wherein a P-N junction which is made to become high-voltage withstanding part, and providing a ring shaped diffused layer around said group of small diffused regions. CONSTITUTION:For example, a P-N junction Jm comprising an N<-> substrate region 1 and a P<+> diffused layer 3 is made to be a high-voltage withstanding part. At this time, in order to weaken the strength of the field which is applied to the junction Jm, impurity diffused layers whose conducting type is the same as the P<+> diffused layer 3 are provided around the P<+> diffused layer 3. As the diffused layers for this purpose, lines of P<+> diffused layers S1 and S2 with a small area are aligned at the positions separated by a specified distance from the diffused layer 3, with a specified space being provided between neighboring small diffused layers. The ring shaped diffused layer R is further formed around the line of diffused layers S2. The arranging position (distance and the like) of each diffused layer is so established that the distance is less than the width of a depletion layer formed by the P-N junctions Jm, JS1, JS2, and JR formed by each diffused layer. In this constitution, the field to be applied to the P-N junction Jm can be effectively weakened, and the chip size can be reduced. If the size is the same, the high withstanding voltage can be obtained.
JP5694380A 1980-04-28 1980-04-28 High-voltage withstanding semiconductor device Pending JPS56153765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5694380A JPS56153765A (en) 1980-04-28 1980-04-28 High-voltage withstanding semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5694380A JPS56153765A (en) 1980-04-28 1980-04-28 High-voltage withstanding semiconductor device

Publications (1)

Publication Number Publication Date
JPS56153765A true JPS56153765A (en) 1981-11-27

Family

ID=13041620

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5694380A Pending JPS56153765A (en) 1980-04-28 1980-04-28 High-voltage withstanding semiconductor device

Country Status (1)

Country Link
JP (1) JPS56153765A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220377A (en) * 1985-03-26 1986-09-30 Matsushita Electronics Corp Semiconductor device
US6044657A (en) * 1997-02-18 2000-04-04 Matsushita Electric Ind Co Ltd Outdoor unit of separate type air conditioner

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61220377A (en) * 1985-03-26 1986-09-30 Matsushita Electronics Corp Semiconductor device
US6044657A (en) * 1997-02-18 2000-04-04 Matsushita Electric Ind Co Ltd Outdoor unit of separate type air conditioner

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