JPS5497381A - Manufacture of junction type field effect transistor - Google Patents

Manufacture of junction type field effect transistor

Info

Publication number
JPS5497381A
JPS5497381A JP463478A JP463478A JPS5497381A JP S5497381 A JPS5497381 A JP S5497381A JP 463478 A JP463478 A JP 463478A JP 463478 A JP463478 A JP 463478A JP S5497381 A JPS5497381 A JP S5497381A
Authority
JP
Japan
Prior art keywords
manufacture
variance
field effect
effect transistor
type field
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP463478A
Other languages
Japanese (ja)
Inventor
Mitsuo Kishimoto
Tetsuo Shirakawa
Masakatsu Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP463478A priority Critical patent/JPS5497381A/en
Publication of JPS5497381A publication Critical patent/JPS5497381A/en
Pending legal-status Critical Current

Links

Landscapes

  • Junction Field-Effect Transistors (AREA)

Abstract

PURPOSE: To reduce the variance of a saturation drain current inside of a Si substrate by forming a well of low density through ion injection.
CONSTITUTION: An opening is made in p-typt Si 1 of 2 to 4Ωcm covered with SiO2 10 and phosphorous ions are injected under conditions of 80keV, 8 degrees-off, and 3×1012 to 16×1012cm-3; diffusion is done at approximate 1200°C for five hours after annealing in dry N2 below 950°C, thereby forming n-type well 11. Next, p+- type layer 4 and channel stopping layers 12 in substrate 1 are formed, and n+-type connection layers 5 and 6 are made before main parts of the JFET are formed. In this way, since the density of drain-source formation region 11 is uniform and low through ion injection and an adequate quantity of ions are injected into the region 11, the variance in saturation drain current lessens and gm can be made large, so that the yield will improve.
COPYRIGHT: (C)1979,JPO&Japio
JP463478A 1978-01-18 1978-01-18 Manufacture of junction type field effect transistor Pending JPS5497381A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP463478A JPS5497381A (en) 1978-01-18 1978-01-18 Manufacture of junction type field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP463478A JPS5497381A (en) 1978-01-18 1978-01-18 Manufacture of junction type field effect transistor

Publications (1)

Publication Number Publication Date
JPS5497381A true JPS5497381A (en) 1979-08-01

Family

ID=11589430

Family Applications (1)

Application Number Title Priority Date Filing Date
JP463478A Pending JPS5497381A (en) 1978-01-18 1978-01-18 Manufacture of junction type field effect transistor

Country Status (1)

Country Link
JP (1) JPS5497381A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63187356U (en) * 1987-05-26 1988-11-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63187356U (en) * 1987-05-26 1988-11-30

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