JPS5487442A - Multi-gate control circuit - Google Patents

Multi-gate control circuit

Info

Publication number
JPS5487442A
JPS5487442A JP15577777A JP15577777A JPS5487442A JP S5487442 A JPS5487442 A JP S5487442A JP 15577777 A JP15577777 A JP 15577777A JP 15577777 A JP15577777 A JP 15577777A JP S5487442 A JPS5487442 A JP S5487442A
Authority
JP
Japan
Prior art keywords
control
bus
input
data
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15577777A
Other languages
Japanese (ja)
Inventor
Akitaka Murozono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15577777A priority Critical patent/JPS5487442A/en
Publication of JPS5487442A publication Critical patent/JPS5487442A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simplify the extension of gates in number and to enable a saimply- constituted circuit, which controls several input-output gates of a microprocessor, etc., to attain control on a bit unit and automatic and periodic control.
CONSTITUTION: The CPU1 is equipped with data bus 11 for transmiting input and output data and control signal line 12 for a control signal outputted from CPU1, with bus 11 and signal line 12 connected together, and also provided with the 1st- class input-output equipment 21 which input data assigned by signal line 12 to bus 11. Further, this CPU1 is equipped with the 2nd-class input-output equipment 22 which is connected to bus 11 and signal line 12 and receives a gate control signal assigned by signal line 12 from bus 11, several gate circuits 41 to 44 which controls the inputting and outputting of data to and from equipment 21, and control line 31 which controls circuits 41 to 44 according to control data inputted to equipment 22. Then, input-output equipment 23 is also provided which controls circuits 41 to 44 by receiving a signal controlling counter circuit 30 among control data of bus 11 and attains automatic and periodic control.
COPYRIGHT: (C)1979,JPO&Japio
JP15577777A 1977-12-23 1977-12-23 Multi-gate control circuit Pending JPS5487442A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15577777A JPS5487442A (en) 1977-12-23 1977-12-23 Multi-gate control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15577777A JPS5487442A (en) 1977-12-23 1977-12-23 Multi-gate control circuit

Publications (1)

Publication Number Publication Date
JPS5487442A true JPS5487442A (en) 1979-07-11

Family

ID=15613170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15577777A Pending JPS5487442A (en) 1977-12-23 1977-12-23 Multi-gate control circuit

Country Status (1)

Country Link
JP (1) JPS5487442A (en)

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