JPS5480086A - Mask aligner - Google Patents
Mask alignerInfo
- Publication number
- JPS5480086A JPS5480086A JP14708677A JP14708677A JPS5480086A JP S5480086 A JPS5480086 A JP S5480086A JP 14708677 A JP14708677 A JP 14708677A JP 14708677 A JP14708677 A JP 14708677A JP S5480086 A JPS5480086 A JP S5480086A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- hole group
- exposure
- blow
- adhered
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Preparing Plates And Mask In Photomechanical Process (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Registering Or Overturning Sheets (AREA)
Abstract
PURPOSE: To diversify the control modes by securing the independent operation for the adhesive force and the sucking force with installation of the 1st and 2nd vent hole groups to perform the blow-up and suction at the center and circumference parts each of the semiconductor wafer.
CONSTITUTION: The 1st vent hole group 10a and 2nd hole group 10b are provided to wafer chuck main body 10 to blow up and suck the center part of semiconductor wafer 15 and the circumference part of wafer 12 respectively. Then wafer 12 is put on body 10, and exposure glass mask 14 containing the pattern of Cr or the like on the surface to be adhered to wafer 12 is put on wafer 12. Thus, the light is irradiated on the resist exposure surface of wafer 12. In this case, hole group 10a and 10b are controlled independently by means of switch unit 16 which is controlled by control system 18, electromagnetic valve 24 and 26 plus pipe arrangement 20 and 22. Thus, wafer 12 is adhered to mask 14 over the entire surface. In this way, both printing and exposure of the pattern becomes possible with a high resolution.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14708677A JPS5480086A (en) | 1977-12-09 | 1977-12-09 | Mask aligner |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14708677A JPS5480086A (en) | 1977-12-09 | 1977-12-09 | Mask aligner |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59005564A Division JPS59155132A (en) | 1984-01-18 | 1984-01-18 | Wafer separating method in exposure |
JP59005563A Division JPS59155131A (en) | 1984-01-18 | 1984-01-18 | Method for contact exposure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5480086A true JPS5480086A (en) | 1979-06-26 |
Family
ID=15422141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14708677A Pending JPS5480086A (en) | 1977-12-09 | 1977-12-09 | Mask aligner |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5480086A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5689744A (en) * | 1979-12-24 | 1981-07-21 | Fujitsu Ltd | X-ray transfer device |
JPS57109330A (en) * | 1980-12-26 | 1982-07-07 | Hitachi Ltd | Mask aliner |
JPS60101097A (en) * | 1983-11-09 | 1985-06-05 | グラフテック株式会社 | Suction apparatus for sheet |
JPS62181440A (en) * | 1985-10-24 | 1987-08-08 | テキサス インスツルメンツ インコ−ポレイテツド | Load locking and manufacture of integrated circuit |
-
1977
- 1977-12-09 JP JP14708677A patent/JPS5480086A/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5689744A (en) * | 1979-12-24 | 1981-07-21 | Fujitsu Ltd | X-ray transfer device |
JPS57109330A (en) * | 1980-12-26 | 1982-07-07 | Hitachi Ltd | Mask aliner |
JPS60101097A (en) * | 1983-11-09 | 1985-06-05 | グラフテック株式会社 | Suction apparatus for sheet |
JPH0585360B2 (en) * | 1983-11-09 | 1993-12-07 | Graphtec Kk | |
JPS62181440A (en) * | 1985-10-24 | 1987-08-08 | テキサス インスツルメンツ インコ−ポレイテツド | Load locking and manufacture of integrated circuit |
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