JPS547866A - Manufacture for semiconductor device - Google Patents
Manufacture for semiconductor deviceInfo
- Publication number
- JPS547866A JPS547866A JP7355877A JP7355877A JPS547866A JP S547866 A JPS547866 A JP S547866A JP 7355877 A JP7355877 A JP 7355877A JP 7355877 A JP7355877 A JP 7355877A JP S547866 A JPS547866 A JP S547866A
- Authority
- JP
- Japan
- Prior art keywords
- manufacture
- semiconductor device
- lead wires
- making coarse
- bond lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Transistors (AREA)
- Wire Bonding (AREA)
Abstract
PURPOSE: To surely bond lead wires, by making coarse the A plane selectively.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7355877A JPS547866A (en) | 1977-06-20 | 1977-06-20 | Manufacture for semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7355877A JPS547866A (en) | 1977-06-20 | 1977-06-20 | Manufacture for semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS547866A true JPS547866A (en) | 1979-01-20 |
Family
ID=13521691
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7355877A Pending JPS547866A (en) | 1977-06-20 | 1977-06-20 | Manufacture for semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS547866A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6249640A (en) * | 1985-08-29 | 1987-03-04 | Mitsubishi Electric Corp | Gold electrode structure |
JPS63249348A (en) * | 1987-04-03 | 1988-10-17 | Nec Corp | Manufacture of semiconductor device |
-
1977
- 1977-06-20 JP JP7355877A patent/JPS547866A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6249640A (en) * | 1985-08-29 | 1987-03-04 | Mitsubishi Electric Corp | Gold electrode structure |
JPH0525176B2 (en) * | 1985-08-29 | 1993-04-12 | Mitsubishi Electric Corp | |
JPS63249348A (en) * | 1987-04-03 | 1988-10-17 | Nec Corp | Manufacture of semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS528785A (en) | Semiconductor device electrode structure | |
JPS5395571A (en) | Semiconductor device | |
JPS5394875A (en) | Package for semiconductor element | |
JPS547866A (en) | Manufacture for semiconductor device | |
JPS5240063A (en) | Lead frame | |
JPS5279658A (en) | Semiconductor device | |
JPS53133371A (en) | Lead frame of plastic package for integrated circuit | |
JPS5334430A (en) | Memory unit | |
JPS525273A (en) | Transistor | |
JPS5348461A (en) | Wire bonder | |
JPS51121272A (en) | Manufacturing method for semiconductor devices | |
JPS5223273A (en) | Method of manufacturing semiconductor element | |
JPS5423466A (en) | Manufacture for semiconductor device | |
JPS53128980A (en) | Positioning device for bonding | |
JPS5279657A (en) | Wire bonding device | |
JPS5279659A (en) | Semiconductor device | |
JPS53124070A (en) | Semiconductor device | |
JPS547869A (en) | Lead bending method of semiconductor device | |
JPS51112292A (en) | Semiconductor device | |
JPS5431277A (en) | Semiconductor device | |
JPS53124066A (en) | Automatic position correction type wire bonding method | |
JPS5370671A (en) | Production of semiconductor device | |
JPS51126062A (en) | Tap short bonding method on wire bonding | |
JPS5355964A (en) | Automatic wire bonding device | |
JPS5240065A (en) | Lead frame |