JPS5474613A - Identifying system of error insetrtion package - Google Patents

Identifying system of error insetrtion package

Info

Publication number
JPS5474613A
JPS5474613A JP14305577A JP14305577A JPS5474613A JP S5474613 A JPS5474613 A JP S5474613A JP 14305577 A JP14305577 A JP 14305577A JP 14305577 A JP14305577 A JP 14305577A JP S5474613 A JPS5474613 A JP S5474613A
Authority
JP
Japan
Prior art keywords
package
circuit
scan
mis
surely
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14305577A
Other languages
Japanese (ja)
Inventor
Kazuo Kurosawa
Shinsuke Kadota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14305577A priority Critical patent/JPS5474613A/en
Publication of JPS5474613A publication Critical patent/JPS5474613A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M3/00—Automatic or semi-automatic exchanges
    • H04M3/08—Indicating faults in circuits or apparatus

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Monitoring And Testing Of Exchanges (AREA)

Abstract

PURPOSE:To enable to detect the mis-insertion simply and surely, by utilizing the fact that the transmission and reception circuit for scan signal i is a closed icrcuit when package insoerted to normal position and it is an open circuit when package inserted at a wrong position. CONSTITUTION:The package 1 prepares the scan input terminal 3 and output terminal 4 in addition to the functional circuit essentially given to the package, and the pattern 5 is conductive between the both terminals. When scan signal is delivered to the package 1 from the central processing control unit CCU, when the package 1 is present at a normal position, the transmission and reception circuit for the scan signsl is a closd circuit and if it is inserted at a wrong position, it is an open circuit. Thus, the detection of mis-insertion can be made simply and surely.
JP14305577A 1977-11-28 1977-11-28 Identifying system of error insetrtion package Pending JPS5474613A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14305577A JPS5474613A (en) 1977-11-28 1977-11-28 Identifying system of error insetrtion package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14305577A JPS5474613A (en) 1977-11-28 1977-11-28 Identifying system of error insetrtion package

Publications (1)

Publication Number Publication Date
JPS5474613A true JPS5474613A (en) 1979-06-14

Family

ID=15329854

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14305577A Pending JPS5474613A (en) 1977-11-28 1977-11-28 Identifying system of error insetrtion package

Country Status (1)

Country Link
JP (1) JPS5474613A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202256A (en) * 1989-01-31 1990-08-10 Nec Corp Switchboard containing package storing position information

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02202256A (en) * 1989-01-31 1990-08-10 Nec Corp Switchboard containing package storing position information

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