JPS5450230A - Terminal system - Google Patents

Terminal system

Info

Publication number
JPS5450230A
JPS5450230A JP11646877A JP11646877A JPS5450230A JP S5450230 A JPS5450230 A JP S5450230A JP 11646877 A JP11646877 A JP 11646877A JP 11646877 A JP11646877 A JP 11646877A JP S5450230 A JPS5450230 A JP S5450230A
Authority
JP
Japan
Prior art keywords
terminal
detecting
controller
cpu3
malfunction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11646877A
Other languages
Japanese (ja)
Inventor
Hiromitsu Sasaki
Susumu Maruyama
Yasutaka Tsutamune
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11646877A priority Critical patent/JPS5450230A/en
Publication of JPS5450230A publication Critical patent/JPS5450230A/en
Pending legal-status Critical Current

Links

Landscapes

  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Cash Registers Or Receiving Machines (AREA)

Abstract

PURPOSE:To assign an arbitrary terminal as a system managment terminal and prevent the error dependent upon malfunction by detecting the signal indicating the insertion of a specific key controlling terminal equipments in a CPU or a terminal controller. CONSTITUTION:Plural terminals 1 are connected to CPU3 directly or through terminal controller 2. Here, when detecting that a specific key defined for sysem management has been inserted into terminal 1, a detecting signal is outputted. then, CPU3 or controller 2 detects this detection signal and assigns arbitraty terminal 1 as system management terminal, and the error dependent upon malfunction can be provented.
JP11646877A 1977-09-28 1977-09-28 Terminal system Pending JPS5450230A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11646877A JPS5450230A (en) 1977-09-28 1977-09-28 Terminal system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11646877A JPS5450230A (en) 1977-09-28 1977-09-28 Terminal system

Publications (1)

Publication Number Publication Date
JPS5450230A true JPS5450230A (en) 1979-04-20

Family

ID=14687842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11646877A Pending JPS5450230A (en) 1977-09-28 1977-09-28 Terminal system

Country Status (1)

Country Link
JP (1) JPS5450230A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103758A (en) * 1980-01-22 1981-08-19 Fujitsu General Ltd Electronic register
JPS5812068A (en) * 1981-07-14 1983-01-24 Omron Tateisi Electronics Co Group managing system for electronic cash register
JPS5969842A (en) * 1982-10-15 1984-04-20 Fujitsu Ltd Method for controlling command of computer system
JPS6029858A (en) * 1983-07-13 1985-02-15 Fuji Electric Co Ltd Input and output control system

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56103758A (en) * 1980-01-22 1981-08-19 Fujitsu General Ltd Electronic register
JPS5812068A (en) * 1981-07-14 1983-01-24 Omron Tateisi Electronics Co Group managing system for electronic cash register
JPS5969842A (en) * 1982-10-15 1984-04-20 Fujitsu Ltd Method for controlling command of computer system
JPS6029858A (en) * 1983-07-13 1985-02-15 Fuji Electric Co Ltd Input and output control system

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