JPS5473565A - Assembling method of semiconductor device and substrate used for such method - Google Patents

Assembling method of semiconductor device and substrate used for such method

Info

Publication number
JPS5473565A
JPS5473565A JP14000977A JP14000977A JPS5473565A JP S5473565 A JPS5473565 A JP S5473565A JP 14000977 A JP14000977 A JP 14000977A JP 14000977 A JP14000977 A JP 14000977A JP S5473565 A JPS5473565 A JP S5473565A
Authority
JP
Japan
Prior art keywords
heat sink
semiconductor device
pellet
collar
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14000977A
Other languages
English (en)
Inventor
Mitsuo Ito
Nobuo Otani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14000977A priority Critical patent/JPS5473565A/ja
Publication of JPS5473565A publication Critical patent/JPS5473565A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP14000977A 1977-11-24 1977-11-24 Assembling method of semiconductor device and substrate used for such method Pending JPS5473565A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14000977A JPS5473565A (en) 1977-11-24 1977-11-24 Assembling method of semiconductor device and substrate used for such method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14000977A JPS5473565A (en) 1977-11-24 1977-11-24 Assembling method of semiconductor device and substrate used for such method

Publications (1)

Publication Number Publication Date
JPS5473565A true JPS5473565A (en) 1979-06-12

Family

ID=15258802

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14000977A Pending JPS5473565A (en) 1977-11-24 1977-11-24 Assembling method of semiconductor device and substrate used for such method

Country Status (1)

Country Link
JP (1) JPS5473565A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02129951A (ja) * 1988-11-09 1990-05-18 Hitachi Ltd 半導体装置の製造方法
JPH07106349A (ja) * 1993-09-30 1995-04-21 Nec Corp 樹脂モールド型半導体装置の製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02129951A (ja) * 1988-11-09 1990-05-18 Hitachi Ltd 半導体装置の製造方法
JPH07106349A (ja) * 1993-09-30 1995-04-21 Nec Corp 樹脂モールド型半導体装置の製造方法

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