JPS57141933A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57141933A
JPS57141933A JP56026501A JP2650181A JPS57141933A JP S57141933 A JPS57141933 A JP S57141933A JP 56026501 A JP56026501 A JP 56026501A JP 2650181 A JP2650181 A JP 2650181A JP S57141933 A JPS57141933 A JP S57141933A
Authority
JP
Japan
Prior art keywords
conductive layer
bump electrode
multipin
connection
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56026501A
Other languages
Japanese (ja)
Inventor
Koichiro Saji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56026501A priority Critical patent/JPS57141933A/en
Publication of JPS57141933A publication Critical patent/JPS57141933A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the breakdown of a multipin element caused by thermal strain and to attain high reliability and low cost for the subject semiconductor device by a method wherein the connection of the bump electrode of the element and an external lead is performed through the intermediary of a conductive layer, located on the insulation film, providing with a bump electrode on the bonded part with the lead. CONSTITUTION:The connection of a multipin element 1 such as an LSI and the like, having a bump electrode 5 consisting of a precious metal, and the external lead 3 is conducted using a conductive layer 7 of the prescribed shape which was formed on an insulative film (tape carrier) of polyimide and the like. A bump electrode 8 is provided at the junction part with the lead 3 of the conductive layer 7, and the connection by the conductive layer 7 is performed using thermo- press welding. Subsequently, a resin sealing process is performed, and this enables to conduct the mounting of the multipin element which is unable to connect on a metal frame. Also, as the thermal distortion can be lessened, and the breakdown and the deterioration of characteristics of the element can be prevented, thereby enabling to obtain a highly reliable device at a low cost.
JP56026501A 1981-02-25 1981-02-25 Semiconductor device Pending JPS57141933A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56026501A JPS57141933A (en) 1981-02-25 1981-02-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56026501A JPS57141933A (en) 1981-02-25 1981-02-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57141933A true JPS57141933A (en) 1982-09-02

Family

ID=12195229

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56026501A Pending JPS57141933A (en) 1981-02-25 1981-02-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57141933A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274333A (en) * 1985-05-29 1986-12-04 Toshiba Corp Semiconductor device
JPH029158A (en) * 1988-06-27 1990-01-12 T & K Internatl Kenkyusho:Kk Resin sealing molding of semiconductor element and semiconductor lead frame therefor
US5159434A (en) * 1990-02-01 1992-10-27 Hitachi, Ltd. Semiconductor device having a particular chip pad structure

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5356970A (en) * 1976-11-02 1978-05-23 Seiko Epson Corp Tape for tape carrier
JPS55158657A (en) * 1979-05-29 1980-12-10 Seiko Epson Corp Electronic device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5356970A (en) * 1976-11-02 1978-05-23 Seiko Epson Corp Tape for tape carrier
JPS55158657A (en) * 1979-05-29 1980-12-10 Seiko Epson Corp Electronic device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61274333A (en) * 1985-05-29 1986-12-04 Toshiba Corp Semiconductor device
JPH029158A (en) * 1988-06-27 1990-01-12 T & K Internatl Kenkyusho:Kk Resin sealing molding of semiconductor element and semiconductor lead frame therefor
US5159434A (en) * 1990-02-01 1992-10-27 Hitachi, Ltd. Semiconductor device having a particular chip pad structure

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