JPS5467350A - Stage tracer - Google Patents

Abstract

PURPOSE: To enable to perform the pepair of failure effectively, by obtaining the operation state of the failure at the occurrence in time sharing manner, through the memorization of the trace information to memory and the write-in stop signal to memroy simultaneously, and through the halt of write-in to memory after a certain time elapsed from the incoming of write-in stop signal.

CONSTITUTION: The monitor signals 7 to 8 of the processor are connected to the input data terminals D₁ to D_i to the memory 1, and the write-in stop condition 6 to the memory 1 is connected to the input data terminal D_o. Further, the address register 2 is connected to the address A of the memory 1, the write-in condition 6 is fed to one input of the AND circuit 5 via the delay circuit 6, and the write-in mode signal 9 and the write-in sampling pulse 10 are fed to another input of the circuit 5. Further, the monitor signals 7 to 8 and the write-in stop condition 6 are memorized in the memory area designated with the register 2, the memory 1 memorizes the write-in stop condition 6 being logic 1 in time sharing manner, and write- in is stopped when the output of the circuit 3 is in logic 1.

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