JPS5444576A - Level display circuit - Google Patents
Level display circuitInfo
- Publication number
- JPS5444576A JPS5444576A JP11087777A JP11087777A JPS5444576A JP S5444576 A JPS5444576 A JP S5444576A JP 11087777 A JP11087777 A JP 11087777A JP 11087777 A JP11087777 A JP 11087777A JP S5444576 A JPS5444576 A JP S5444576A
- Authority
- JP
- Japan
- Prior art keywords
- peak value
- supplied
- value
- signal
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
PURPOSE: To enable the maximum value of the peak value of the latest audio input to be accurately and promptly known by displaying the analong quantity and peak value corresponding to input analog signal simultaneously and making the displaying of the peak value resttable.
CONSTITUTION: Input analog signal is envelope-detected in the detection circuit 3 of a voltage-pulse number converting circuit 10, and is compared with the saw tooth wave having undergone frequency division 8 and conversion 9 of the reference clock pulse Pa from a reference oscillator 7 in a comparator 6, whose output is then supplied to an AND gate 11 and is serially converted to the pulse signal Pf of the level corresponding to the input analog signal. This pulse signal Pf is supplied to a level display device 16 and is analog-displayed by the element numbers S1, S2... of its liquid crystal display plate. On the other hand, the signal Pf is supplied to a detection circuit 20 and is supplied to an AND gate 24 via FF21 to obtain the maximum value P1 of the peak value. This value is then added to the time delay pulse signal Pf in an OR gate 13 and is next supplied to the level display device 16, where it is displayed as the peak value together with the analog value. In this way, the latest peak value may be known at all times by resetting.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11087777A JPS5444576A (en) | 1977-09-14 | 1977-09-14 | Level display circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11087777A JPS5444576A (en) | 1977-09-14 | 1977-09-14 | Level display circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5444576A true JPS5444576A (en) | 1979-04-09 |
Family
ID=14546954
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP11087777A Pending JPS5444576A (en) | 1977-09-14 | 1977-09-14 | Level display circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5444576A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58125874U (en) * | 1982-02-18 | 1983-08-26 | 松下電器産業株式会社 | level display device |
US4679042A (en) * | 1985-04-22 | 1987-07-07 | The Grass Valley Group, Inc. | Bar/dot level meter |
-
1977
- 1977-09-14 JP JP11087777A patent/JPS5444576A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58125874U (en) * | 1982-02-18 | 1983-08-26 | 松下電器産業株式会社 | level display device |
US4679042A (en) * | 1985-04-22 | 1987-07-07 | The Grass Valley Group, Inc. | Bar/dot level meter |
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