JPS5623024A - Frequency multiplication circuit - Google Patents
Frequency multiplication circuitInfo
- Publication number
- JPS5623024A JPS5623024A JP9871879A JP9871879A JPS5623024A JP S5623024 A JPS5623024 A JP S5623024A JP 9871879 A JP9871879 A JP 9871879A JP 9871879 A JP9871879 A JP 9871879A JP S5623024 A JPS5623024 A JP S5623024A
- Authority
- JP
- Japan
- Prior art keywords
- counter
- output
- signal
- circuit
- value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To obtain the frequency multiplication circuit in which accurate n-times frequency can be obtained, by compensating the value of the deciaml point or below of the measurement value of the period of input pulse. CONSTITUTION:The timing circuit 6 producing the set signal S and reset signal R at the leading of the input signal fi resets the 1/n frequency divider 7 and the up- counter 3 with the signal R. After that, the counter 3 counts the 1/n output of the output of the high frequency oscillator 1. The count value of the counter 3, e.g. D is set to the down-counter 5 via the register 9 with up-counter with the signal S from the circuit 6. This counter 5 produces output every time the output of the high frequency oscillator 1 is counted by D. The correction circuit 8 switches the set value to the down-counter 5 to D+1 according to the error component of the frequency divider 7 and controls the register 9 so that the output of the counter 5 can be output accurately by (n) pulses ar one period of the input signal fi.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9871879A JPS5623024A (en) | 1979-08-03 | 1979-08-03 | Frequency multiplication circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9871879A JPS5623024A (en) | 1979-08-03 | 1979-08-03 | Frequency multiplication circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5623024A true JPS5623024A (en) | 1981-03-04 |
JPH028492B2 JPH028492B2 (en) | 1990-02-26 |
Family
ID=14227294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9871879A Granted JPS5623024A (en) | 1979-08-03 | 1979-08-03 | Frequency multiplication circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5623024A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101907U (en) * | 1981-12-30 | 1983-07-11 | 大和ハウス工業株式会社 | partition |
JPS60201719A (en) * | 1984-03-27 | 1985-10-12 | Oval Eng Co Ltd | Frequency multiplying circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52122733A (en) * | 1976-04-07 | 1977-10-15 | Toshiba Corp | Pulse line converter |
-
1979
- 1979-08-03 JP JP9871879A patent/JPS5623024A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS52122733A (en) * | 1976-04-07 | 1977-10-15 | Toshiba Corp | Pulse line converter |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101907U (en) * | 1981-12-30 | 1983-07-11 | 大和ハウス工業株式会社 | partition |
JPS60201719A (en) * | 1984-03-27 | 1985-10-12 | Oval Eng Co Ltd | Frequency multiplying circuit |
Also Published As
Publication number | Publication date |
---|---|
JPH028492B2 (en) | 1990-02-26 |
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