JPS58125874U - level display device - Google Patents
level display deviceInfo
- Publication number
- JPS58125874U JPS58125874U JP2216282U JP2216282U JPS58125874U JP S58125874 U JPS58125874 U JP S58125874U JP 2216282 U JP2216282 U JP 2216282U JP 2216282 U JP2216282 U JP 2216282U JP S58125874 U JPS58125874 U JP S58125874U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- display
- base
- resistor
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Measurement Of Current Or Voltage (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のレベル表示装置を示す回路図、第２図は
ミューティング回路を接続した時の回路図、第３図は本
考案のレベル表示装置の一実施例を示す回路図、第４図
はミューティング回路を接続した場合の回路図である。
１・・・・・・″制御部、２・・・・・・信号入力端子
、３・・・・・・表示部、１４・・・・・・ミューティ
ラグ信号の入力端子、２５・・・・・・ピークホールド
リセット部、２６・・・・・・抵抗、２７・・・・・・
コンデンサ、２８．２９・・・・・・抵抗、３１・・・
・・・ＰＮＰ型のトランジスタ、３２・・・・・・ＮＰ
Ｎ型のトランジスタ。Fig. 1 is a circuit diagram showing a conventional level display device, Fig. 2 is a circuit diagram when a muting circuit is connected, Fig. 3 is a circuit diagram showing an embodiment of the level display device of the present invention, and Fig. 4 is a circuit diagram showing a conventional level display device. The figure is a circuit diagram when a muting circuit is connected. 1...''control section, 2...signal input terminal, 3...display section, 14...muti-lag signal input terminal, 25... ...Peak hold reset section, 26...Resistor, 27...
Capacitor, 28.29... Resistor, 31...
...PNP type transistor, 32...NP
N-type transistor.
Claims (1)
力側に前記表示部を接続し、可聴周波数の信号を入力し
てこの入力信号レベルをアナログ−ディジタル変換し、
変換出力によって前記表示部を駆動し入力信号レベルに
応じて順次表示器を点灯させるとともに入力信号レベル
の最大値に対応した表示器のみを継続点灯させる制御部
と、前記制御部のリセット端子に接続されリセット信号
を印加するピークホールドリセット部とを備え、このピ
ークホールドリセット部は電源とアース間を第１の抵抗
、コンデンサの順の直列回路で接続し、また同様に電源
とアース間を第２の抵抗、第３の抵抗の順の直列回路で
接続し、ＰＮＰ型の第１のトランジスタのエミッタを前
記第１の抵抗とコンデンサの接続点に、同トランジスタ
のベースを前記第２、第３の抵抗の接続上にそれぞれ接
続し、このトランジスタのコレクタをＮＰＮ型の第２の
トランジスタのベースに接続し、第２のトランジスタの
コレクタを第１のトランジスタのベースに、第２のトラ
ンジスタのエミッタをアースにそれぞれ接続し、前記第
２のトランジスタのベースをミューティング信号入力端
となして形成し、前記第２のトランジスタのコレクタに
発生する定期的なパルス信号を制御部のリセット端子に
入力させ、入力レベルの最大値に対応して継続点灯され
ている表示器を消灯させるように構成したことを特徴と
するレベル表示装置。A display section having a plurality of display devices arranged in a row, the display section being connected to the output side, inputting an audio frequency signal and converting the input signal level from analog to digital;
A control unit that drives the display unit using the conversion output to sequentially light up the display units according to the input signal level and continues to light up only the display unit corresponding to the maximum value of the input signal level, and is connected to a reset terminal of the control unit. The peak hold reset section connects the power supply and the ground with a series circuit consisting of a first resistor and a capacitor, and similarly connects the power supply and the ground with a second series circuit. and a third resistor are connected in a series circuit, with the emitter of the first PNP transistor connected to the connection point between the first resistor and the capacitor, and the base of the transistor connected to the second and third resistors. The collector of this transistor is connected to the base of a second transistor of NPN type, the collector of the second transistor is connected to the base of the first transistor, and the emitter of the second transistor is connected to the ground. , the base of the second transistor is formed as a muting signal input terminal, and a periodic pulse signal generated at the collector of the second transistor is inputted to the reset terminal of the control section, and the input A level display device characterized in that it is configured to turn off a continuously lit indicator in response to a maximum level value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216282U JPS58125874U (en) | 1982-02-18 | 1982-02-18 | level display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2216282U JPS58125874U (en) | 1982-02-18 | 1982-02-18 | level display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58125874U true JPS58125874U (en) | 1983-08-26 |
Family
ID=30034257
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2216282U Pending JPS58125874U (en) | 1982-02-18 | 1982-02-18 | level display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58125874U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4411704Y1 (en) * | 1966-04-26 | 1969-05-15 | ||
| JPS5444576A (en) * | 1977-09-14 | 1979-04-09 | Sony Corp | Level display circuit |
-
1982
- 1982-02-18 JP JP2216282U patent/JPS58125874U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4411704Y1 (en) * | 1966-04-26 | 1969-05-15 | ||
| JPS5444576A (en) * | 1977-09-14 | 1979-04-09 | Sony Corp | Level display circuit |
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