JPS5429588A - Manufacture for semicomdudtor device - Google Patents

Manufacture for semicomdudtor device

Info

Publication number
JPS5429588A
JPS5429588A JP9531377A JP9531377A JPS5429588A JP S5429588 A JPS5429588 A JP S5429588A JP 9531377 A JP9531377 A JP 9531377A JP 9531377 A JP9531377 A JP 9531377A JP S5429588 A JPS5429588 A JP S5429588A
Authority
JP
Japan
Prior art keywords
semicomdudtor
manufacture
plating film
plating
simplifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9531377A
Other languages
Japanese (ja)
Inventor
Masaru Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9531377A priority Critical patent/JPS5429588A/en
Publication of JPS5429588A publication Critical patent/JPS5429588A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To increase the reliability of products, by eliminating the plating film failure of the through-hole region, simplifying the wiring process time processing, and by strengthening the bonding of the plating film, in manufacturing the metallic film circuit wiring with electric plating method.
COPYRIGHT: (C)1979,JPO&Japio
JP9531377A 1977-08-08 1977-08-08 Manufacture for semicomdudtor device Pending JPS5429588A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9531377A JPS5429588A (en) 1977-08-08 1977-08-08 Manufacture for semicomdudtor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9531377A JPS5429588A (en) 1977-08-08 1977-08-08 Manufacture for semicomdudtor device

Publications (1)

Publication Number Publication Date
JPS5429588A true JPS5429588A (en) 1979-03-05

Family

ID=14134257

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9531377A Pending JPS5429588A (en) 1977-08-08 1977-08-08 Manufacture for semicomdudtor device

Country Status (1)

Country Link
JP (1) JPS5429588A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6352490A (en) * 1986-08-22 1988-03-05 Toshiba Corp Glass-sealed light-emitting semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6352490A (en) * 1986-08-22 1988-03-05 Toshiba Corp Glass-sealed light-emitting semiconductor device

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