JPS54161860A - One-chip microcomputer featuring test mode setting function - Google Patents
One-chip microcomputer featuring test mode setting functionInfo
- Publication number
- JPS54161860A JPS54161860A JP7119078A JP7119078A JPS54161860A JP S54161860 A JPS54161860 A JP S54161860A JP 7119078 A JP7119078 A JP 7119078A JP 7119078 A JP7119078 A JP 7119078A JP S54161860 A JPS54161860 A JP S54161860A
- Authority
- JP
- Japan
- Prior art keywords
- test
- reset
- gates
- signal
- test mode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Executing Machine-Instructions (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- Microcomputers (AREA)
Abstract
PURPOSE: To perform the test for the memory unit by applying the signals to the prescribed terminal during the reset state and thus securing free setting of the test mode.
CONSTITUTION: Signal TEST is set to logic O while signal RESET is logic O, FF17 is set via NOR circuit 19-1. Then if signal RESET is set to "1" under these conditions, control part 16 features the test mode mask ROM3 damp. After this, part 16 features the application mode of the external order with signal TEST set to "1". At the same time, signal RESET is once set to "0" to set TEST to "1". And if RESET is set to "1" under these conditions, FF17 is reset via NOR circuit 19-2. In the mode of ROM damp, multiplexer 18 closes gates 36W39 and opens gates 40W43 to deliver the memory contents from input/output port 15. When the external order is applied, gates 20W27 are closed with gates 28W35 opened. And the decoding process is given through the multiplexer.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53071190A JPS6029980B2 (en) | 1978-06-13 | 1978-06-13 | One-chip microcomputer with test mode setting function |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53071190A JPS6029980B2 (en) | 1978-06-13 | 1978-06-13 | One-chip microcomputer with test mode setting function |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54161860A true JPS54161860A (en) | 1979-12-21 |
JPS6029980B2 JPS6029980B2 (en) | 1985-07-13 |
Family
ID=13453486
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53071190A Expired JPS6029980B2 (en) | 1978-06-13 | 1978-06-13 | One-chip microcomputer with test mode setting function |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6029980B2 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56155452A (en) * | 1980-05-02 | 1981-12-01 | Matsushita Electronics Corp | Testing method for large scale integrated circuit device |
JPS57123455A (en) * | 1981-01-23 | 1982-07-31 | Nec Corp | Instruction executing device |
JPS5864584A (en) * | 1981-10-14 | 1983-04-16 | アマノ株式会社 | Time recorder |
JPS58105354A (en) * | 1981-12-16 | 1983-06-23 | Hitachi Ltd | Computer controlling system |
JPS58163048A (en) * | 1982-03-23 | 1983-09-27 | Oki Electric Ind Co Ltd | Integrated circuit with checking function of internal signal |
JPS60134350A (en) * | 1983-12-22 | 1985-07-17 | Nec Corp | Single chip microcomputer |
JPS6155747A (en) * | 1984-08-28 | 1986-03-20 | Toshiba Corp | Digital integrated circuit having data transfer control circuit |
JPS62179038A (en) * | 1986-02-03 | 1987-08-06 | Matsushita Electric Ind Co Ltd | Rom readout circuit for microcomputer |
-
1978
- 1978-06-13 JP JP53071190A patent/JPS6029980B2/en not_active Expired
Cited By (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6160460B2 (en) * | 1980-05-02 | 1986-12-20 | Matsushita Electronics Corp | |
JPS56155452A (en) * | 1980-05-02 | 1981-12-01 | Matsushita Electronics Corp | Testing method for large scale integrated circuit device |
JPS57123455A (en) * | 1981-01-23 | 1982-07-31 | Nec Corp | Instruction executing device |
JPH0157824B2 (en) * | 1981-01-23 | 1989-12-07 | Nippon Electric Co | |
JPS5864584A (en) * | 1981-10-14 | 1983-04-16 | アマノ株式会社 | Time recorder |
JPS58105354A (en) * | 1981-12-16 | 1983-06-23 | Hitachi Ltd | Computer controlling system |
JPH055133B2 (en) * | 1981-12-16 | 1993-01-21 | Hitachi Seisakusho Kk | |
JPS6248862B2 (en) * | 1982-03-23 | 1987-10-15 | Oki Electric Ind Co Ltd | |
JPS58163048A (en) * | 1982-03-23 | 1983-09-27 | Oki Electric Ind Co Ltd | Integrated circuit with checking function of internal signal |
JPH0120779B2 (en) * | 1983-12-22 | 1989-04-18 | Nippon Electric Co | |
JPS60134350A (en) * | 1983-12-22 | 1985-07-17 | Nec Corp | Single chip microcomputer |
JPS6155747A (en) * | 1984-08-28 | 1986-03-20 | Toshiba Corp | Digital integrated circuit having data transfer control circuit |
JPS62179038A (en) * | 1986-02-03 | 1987-08-06 | Matsushita Electric Ind Co Ltd | Rom readout circuit for microcomputer |
Also Published As
Publication number | Publication date |
---|---|
JPS6029980B2 (en) | 1985-07-13 |
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