JPS54152849A - Binary coding device - Google Patents

Binary coding device

Info

Publication number
JPS54152849A
JPS54152849A JP6099678A JP6099678A JPS54152849A JP S54152849 A JPS54152849 A JP S54152849A JP 6099678 A JP6099678 A JP 6099678A JP 6099678 A JP6099678 A JP 6099678A JP S54152849 A JPS54152849 A JP S54152849A
Authority
JP
Japan
Prior art keywords
voltage
peak value
value detecting
minimum value
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6099678A
Other languages
Japanese (ja)
Inventor
Kenji Nakamura
Shinji Matsuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6099678A priority Critical patent/JPS54152849A/en
Publication of JPS54152849A publication Critical patent/JPS54152849A/en
Pending legal-status Critical Current

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Landscapes

  • Picture Signal Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE: To secure the detection of the accurate peak value regardless of the voltage fluctuation caused by the temperature drift of the video signals by charging the peak value detecting capacitor with sufficiently higher voltage than the video input signal at the minimum value detecting circuit part.
CONSTITUTION: At the minimum value detecting circuit part comprising diode D5, analog switch AS8 and As9, peak value detecting capacitor C6, resistances R49∼ R51 and amplifier R each, voltage V2 formed with R50 and R51 via the voltage divider is charged to C6 by turning on AS9. And the discharging is given from C6 to Vp (output voltage of amplifier P) through D5 when AS8 is turned on, and this discharging is performed every time Vp lower than potential of C6 is supplied. Thus, the minimum value of Vp during the sampling period remains at C6, and output VR is obtained through R49 and R. In such circuit constitution, the operation to swing the video signal positive and negative which is hitherto required to detect the peak value can be omitted, and accordingly the accurate peak value can be detected even in case the voltage fluctuataion may be caused by the temperature drift to the video signals. As a result, the threshold level can always be secured to obtain the proper binary coding output V0.
COPYRIGHT: (C)1979,JPO&Japio
JP6099678A 1978-05-24 1978-05-24 Binary coding device Pending JPS54152849A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6099678A JPS54152849A (en) 1978-05-24 1978-05-24 Binary coding device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6099678A JPS54152849A (en) 1978-05-24 1978-05-24 Binary coding device

Publications (1)

Publication Number Publication Date
JPS54152849A true JPS54152849A (en) 1979-12-01

Family

ID=13158543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6099678A Pending JPS54152849A (en) 1978-05-24 1978-05-24 Binary coding device

Country Status (1)

Country Link
JP (1) JPS54152849A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150222A (en) * 1981-03-12 1982-09-17 Olympus Optical Co Ltd Binary signal converting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57150222A (en) * 1981-03-12 1982-09-17 Olympus Optical Co Ltd Binary signal converting circuit

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