JPS57150222A - Binary signal converting circuit - Google Patents

Binary signal converting circuit

Info

Publication number
JPS57150222A
JPS57150222A JP3448881A JP3448881A JPS57150222A JP S57150222 A JPS57150222 A JP S57150222A JP 3448881 A JP3448881 A JP 3448881A JP 3448881 A JP3448881 A JP 3448881A JP S57150222 A JPS57150222 A JP S57150222A
Authority
JP
Japan
Prior art keywords
maximum value
signal
supplied
differential amplifier
binary signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3448881A
Other languages
Japanese (ja)
Inventor
Masatoshi Ida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Corp
Olympus Optical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Corp, Olympus Optical Co Ltd filed Critical Olympus Corp
Priority to JP3448881A priority Critical patent/JPS57150222A/en
Publication of JPS57150222A publication Critical patent/JPS57150222A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/08—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding
    • H03K5/082—Shaping pulses by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding with an adaptive threshold

Abstract

PURPOSE:To always obtain a proper binary signal, by varying a threshold level signal in accordance with magnitude of the minimum value and the maximum value in a prescribed period of a time series signal, and converting the time series signal to a binary signal. CONSTITUTION:A signal inputted to a terminal 1 is supplied to a differential amplifier 4. An output of the differential amplifier 4 is provided to a maximum value detecting circuit 7. The maximum value detecting circuit 7 detects the maximum value in a prescribed period and holds it for a constant interval of time. A signal holding the maximum value is amplified by a differential amplifier 9 again and is supplied to an adding circuit 10. As a result, the minimum value of the input signal is supplied to the adding circuit 10. Also, the maximum value of the input signal is also detected by a maximum value detecting circuit 11 and is supplied to the adding circuit 10. Accordingly, the maximum value and the minimum value of the input signal are added. This added result is divided by a voltage divider 12, is made to a threshold level, and is provided to a comparator 2.
JP3448881A 1981-03-12 1981-03-12 Binary signal converting circuit Pending JPS57150222A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3448881A JPS57150222A (en) 1981-03-12 1981-03-12 Binary signal converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3448881A JPS57150222A (en) 1981-03-12 1981-03-12 Binary signal converting circuit

Publications (1)

Publication Number Publication Date
JPS57150222A true JPS57150222A (en) 1982-09-17

Family

ID=12415618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3448881A Pending JPS57150222A (en) 1981-03-12 1981-03-12 Binary signal converting circuit

Country Status (1)

Country Link
JP (1) JPS57150222A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152849A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Binary coding device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54152849A (en) * 1978-05-24 1979-12-01 Hitachi Ltd Binary coding device

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