JPS54151332A - Buffer memory control unit - Google Patents

Buffer memory control unit

Info

Publication number
JPS54151332A
JPS54151332A JP6026778A JP6026778A JPS54151332A JP S54151332 A JPS54151332 A JP S54151332A JP 6026778 A JP6026778 A JP 6026778A JP 6026778 A JP6026778 A JP 6026778A JP S54151332 A JPS54151332 A JP S54151332A
Authority
JP
Japan
Prior art keywords
block
buffer memory
access
bus
advance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6026778A
Other languages
Japanese (ja)
Other versions
JPS6136263B2 (en
Inventor
Masanobu Akagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6026778A priority Critical patent/JPS54151332A/en
Publication of JPS54151332A publication Critical patent/JPS54151332A/en
Publication of JPS6136263B2 publication Critical patent/JPS6136263B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the performance of the data processor, by providing the acces bit to the managing table of the buffer memory and taking an advance the block having the greater possibility to be accessed in future in the buffer memory.
CONSTITUTION: The access bit read out from the access managing section 2 is checked. If the value is in logical 0, it is shown that the corresponding block is a block taken in advance before and the presence of first access is possible. Then, the adjacent block having greater possibility to be accessed in future should be taken in advance. Thus, after the access bit of the corresponding block is rewritten in the logic 1 with the data given with the bus 800-1, the output of the selector 500 is given to the adder 700 with the bus 500-1, and the result of addition by the block length is fetched from the bus 700-1 to the auxiliary address register 400. Further, the managing table 200 is checked with the auxiliary address.
COPYRIGHT: (C)1979,JPO&Japio
JP6026778A 1978-05-19 1978-05-19 Buffer memory control unit Granted JPS54151332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6026778A JPS54151332A (en) 1978-05-19 1978-05-19 Buffer memory control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6026778A JPS54151332A (en) 1978-05-19 1978-05-19 Buffer memory control unit

Publications (2)

Publication Number Publication Date
JPS54151332A true JPS54151332A (en) 1979-11-28
JPS6136263B2 JPS6136263B2 (en) 1986-08-18

Family

ID=13137192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6026778A Granted JPS54151332A (en) 1978-05-19 1978-05-19 Buffer memory control unit

Country Status (1)

Country Link
JP (1) JPS54151332A (en)

Also Published As

Publication number Publication date
JPS6136263B2 (en) 1986-08-18

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