JPS54144872A - Electronic circuit device - Google Patents

Electronic circuit device

Info

Publication number
JPS54144872A
JPS54144872A JP5337778A JP5337778A JPS54144872A JP S54144872 A JPS54144872 A JP S54144872A JP 5337778 A JP5337778 A JP 5337778A JP 5337778 A JP5337778 A JP 5337778A JP S54144872 A JPS54144872 A JP S54144872A
Authority
JP
Japan
Prior art keywords
lead
chip
resin
frame
frames
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5337778A
Other languages
English (en)
Inventor
Takao Sumoto
Toshio Asaoka
Takeshi Fujiwara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP5337778A priority Critical patent/JPS54144872A/ja
Publication of JPS54144872A publication Critical patent/JPS54144872A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP5337778A 1978-05-04 1978-05-04 Electronic circuit device Pending JPS54144872A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5337778A JPS54144872A (en) 1978-05-04 1978-05-04 Electronic circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5337778A JPS54144872A (en) 1978-05-04 1978-05-04 Electronic circuit device

Publications (1)

Publication Number Publication Date
JPS54144872A true JPS54144872A (en) 1979-11-12

Family

ID=12941122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5337778A Pending JPS54144872A (en) 1978-05-04 1978-05-04 Electronic circuit device

Country Status (1)

Country Link
JP (1) JPS54144872A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57148362A (en) * 1981-03-10 1982-09-13 Nec Corp Semiconductor device
JPS62105458A (ja) * 1985-10-31 1987-05-15 Shinko Electric Ind Co Ltd 半導体装置用パツケ−ジ
JPS6348852A (ja) * 1986-08-19 1988-03-01 Toshiba Corp 大規模集積回路装置
WO1988006348A1 (en) * 1987-02-20 1988-08-25 Lsi Logic Corporation Integrated circuit package assembly
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
JPH02105450A (ja) * 1988-10-13 1990-04-18 Nec Corp 半導体装置
US4984062A (en) * 1987-03-30 1991-01-08 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device
US5034350A (en) * 1987-09-23 1991-07-23 Sgs Thomson Microelectronics S.R.L. Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
US5101324A (en) * 1989-03-02 1992-03-31 Seiko Epson Corporation Structure, method of, and apparatus for mounting semiconductor devices
US5347429A (en) * 1990-11-14 1994-09-13 Hitachi, Ltd. Plastic-molded-type semiconductor device

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57148362A (en) * 1981-03-10 1982-09-13 Nec Corp Semiconductor device
JPS6342860B2 (ja) * 1981-03-10 1988-08-25 Nippon Electric Co
JPS62105458A (ja) * 1985-10-31 1987-05-15 Shinko Electric Ind Co Ltd 半導体装置用パツケ−ジ
JPS6348852A (ja) * 1986-08-19 1988-03-01 Toshiba Corp 大規模集積回路装置
WO1988006348A1 (en) * 1987-02-20 1988-08-25 Lsi Logic Corporation Integrated circuit package assembly
US4984062A (en) * 1987-03-30 1991-01-08 Mitsubishi Denki Kabushiki Kaisha Packaged semiconductor device
US5034350A (en) * 1987-09-23 1991-07-23 Sgs Thomson Microelectronics S.R.L. Semiconductor device package with dies mounted on both sides of the central pad of a metal frame
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
JPH02105450A (ja) * 1988-10-13 1990-04-18 Nec Corp 半導体装置
US5101324A (en) * 1989-03-02 1992-03-31 Seiko Epson Corporation Structure, method of, and apparatus for mounting semiconductor devices
US5347429A (en) * 1990-11-14 1994-09-13 Hitachi, Ltd. Plastic-molded-type semiconductor device

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