JPS54142039A - Microprogram control computer system - Google Patents

Microprogram control computer system

Info

Publication number
JPS54142039A
JPS54142039A JP4934078A JP4934078A JPS54142039A JP S54142039 A JPS54142039 A JP S54142039A JP 4934078 A JP4934078 A JP 4934078A JP 4934078 A JP4934078 A JP 4934078A JP S54142039 A JPS54142039 A JP S54142039A
Authority
JP
Japan
Prior art keywords
memory
data transfer
input
cpu1
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4934078A
Other languages
Japanese (ja)
Inventor
Tadahiro Yanagisawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4934078A priority Critical patent/JPS54142039A/en
Publication of JPS54142039A publication Critical patent/JPS54142039A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize the data transfer between the memory and the input/output bus bar without giving any effect to the operation of CPU by starting the data transfer between the memory and the input/output bus right afrer the start of the CPU's internal operation.
CONSTITUTION: For the moving body of the microcomputer, the internal operation time of CPU1 is longer (usually 5W50 times) than the data transfer time between memory 3 and CPU1. And the data transfer period between memory 3 and process input device 4 or process output device 5 is usually more than several tens of ms. Thus, the data transfer is started between memory 3 and input/output bus bar 12 right after the start of CPU1's internal operation and then finished until end of the internal action of the CPU. As a result, the competition is avoided between CPU3 and input/output controller 6B, thus realizing a direct connection between CPU1 and common bus 11. In other words, the CPU is never blocked for its operation by controller 6B with no existence of such elements as to delay the operation.
COPYRIGHT: (C)1979,JPO&Japio
JP4934078A 1978-04-27 1978-04-27 Microprogram control computer system Pending JPS54142039A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4934078A JPS54142039A (en) 1978-04-27 1978-04-27 Microprogram control computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4934078A JPS54142039A (en) 1978-04-27 1978-04-27 Microprogram control computer system

Publications (1)

Publication Number Publication Date
JPS54142039A true JPS54142039A (en) 1979-11-05

Family

ID=12828260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4934078A Pending JPS54142039A (en) 1978-04-27 1978-04-27 Microprogram control computer system

Country Status (1)

Country Link
JP (1) JPS54142039A (en)

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