JPS54139764A - Electronic watch - Google Patents

Abstract

PURPOSE:To perform abnormality detection of divided outputs and adequate disposition for this by comparing the time constant of an integrated circuit by the outputs of the specified frequency dividing stage and the divided outputs and producing the period delay signal of the divided outputs. CONSTITUTION:A transmission gate GT is controlled by the outputs of the dividing 1, 2 stages F1, F2 of a grequency divider 2 being applied to the NOR gate G1 of a detecting circuit 5 and the capacitor of the integrated circuit charged at this timing discharges the capacitor C at the time constant determined by a resistance R. This discharge voltage and the reference voltage through a transistor Tr1 which is conducted by the output of the dividing 3 stage F3 are compared in a comparator 18. When the divided outputs of the dividing 2nd stage become longer as the supply voltage lowers and dividing becomes abnormal, then the output of the comparator 18 inverts to a high level, causing the set output to be latched in a D type FFF4 and providing an abnormality detection signal. When the gate is controlled by this signal, the abnormal detection is displayed and the adequate preventive disposition against divided output stop and watch function stop may be taken.