JPS5517426A - Initial value set circuit for electronic watch - Google Patents

Initial value set circuit for electronic watch

Info

Publication number
JPS5517426A
JPS5517426A JP9014978A JP9014978A JPS5517426A JP S5517426 A JPS5517426 A JP S5517426A JP 9014978 A JP9014978 A JP 9014978A JP 9014978 A JP9014978 A JP 9014978A JP S5517426 A JPS5517426 A JP S5517426A
Authority
JP
Japan
Prior art keywords
oscillation
output
power supply
vss
vdd
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9014978A
Other languages
Japanese (ja)
Inventor
Koichi Oota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Citizen Watch Co Ltd
Original Assignee
Citizen Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co Ltd filed Critical Citizen Watch Co Ltd
Priority to JP9014978A priority Critical patent/JPS5517426A/en
Publication of JPS5517426A publication Critical patent/JPS5517426A/en
Pending legal-status Critical Current

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  • Electric Clocks (AREA)
  • Electromechanical Clocks (AREA)

Abstract

PURPOSE: To set the initial value of FF including frequency demultiplier and to enable to achieve small volume with less components and low cost, by detecting the time lag until the power supply is applied and the crystal starts oscillation.
CONSTITUTION: The oscillation section a is gradually oscillated when the power supply is applied, and the output is about intermediate between the power supply voltage VDD and VSS when it is not in oscillation and the output is the amplitude Schmitt trigger circuit b is set higher than Vm, the output of trigger b is at VSS when not in oscillation and it is pulsive when the oscillation amplitude exceeds VTH. The output Q is at VDD of the set priority FF d from the application of power supply till the time when the oscillation amplitude exceeds VTH. The counter circuits e to i are in reset state, and when the oscillation voltag exceeds VTH, the output Q of FF d is changed from VDD to VSS to bring the circuits e to i into frequency dividable.
COPYRIGHT: (C)1980,JPO&Japio
JP9014978A 1978-07-24 1978-07-24 Initial value set circuit for electronic watch Pending JPS5517426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9014978A JPS5517426A (en) 1978-07-24 1978-07-24 Initial value set circuit for electronic watch

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9014978A JPS5517426A (en) 1978-07-24 1978-07-24 Initial value set circuit for electronic watch

Publications (1)

Publication Number Publication Date
JPS5517426A true JPS5517426A (en) 1980-02-06

Family

ID=13990435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9014978A Pending JPS5517426A (en) 1978-07-24 1978-07-24 Initial value set circuit for electronic watch

Country Status (1)

Country Link
JP (1) JPS5517426A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57104882A (en) * 1980-12-22 1982-06-30 Seiko Epson Corp Power on clear circuit in electronic watch

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57104882A (en) * 1980-12-22 1982-06-30 Seiko Epson Corp Power on clear circuit in electronic watch

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