JPS54139344A - Clock-system static memory - Google Patents

Clock-system static memory

Info

Publication number
JPS54139344A
JPS54139344A JP3178379A JP3178379A JPS54139344A JP S54139344 A JPS54139344 A JP S54139344A JP 3178379 A JP3178379 A JP 3178379A JP 3178379 A JP3178379 A JP 3178379A JP S54139344 A JPS54139344 A JP S54139344A
Authority
JP
Japan
Prior art keywords
data
line
lines
gate
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3178379A
Other languages
English (en)
Other versions
JPS5751192B2 (ja
Inventor
Toshishige Ando
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of JPS54139344A publication Critical patent/JPS54139344A/ja
Publication of JPS5751192B2 publication Critical patent/JPS5751192B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
JP3178379A 1978-03-20 1979-03-20 Clock-system static memory Granted JPS54139344A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/890,627 US4150441A (en) 1978-03-20 1978-03-20 Clocked static memory

Publications (2)

Publication Number Publication Date
JPS54139344A true JPS54139344A (en) 1979-10-29
JPS5751192B2 JPS5751192B2 (ja) 1982-10-30

Family

ID=25396914

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3178379A Granted JPS54139344A (en) 1978-03-20 1979-03-20 Clock-system static memory

Country Status (4)

Country Link
US (1) US4150441A (ja)
EP (1) EP0004444B1 (ja)
JP (1) JPS54139344A (ja)
DE (1) DE2962765D1 (ja)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56146964U (ja) * 1980-04-07 1981-11-05
JPS5819791A (ja) * 1981-07-27 1983-02-04 Seiko Epson Corp 半導体記憶装置
JPS6061985A (ja) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp 半導体記憶装置
JPS6061986A (ja) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp 半導体記憶装置
JPS60119691A (ja) * 1983-11-30 1985-06-27 Nec Corp メモリ回路
JPS60182096A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd 半導体記憶装置
JPS62103894A (ja) * 1985-10-30 1987-05-14 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 読取り完了信号発生回路

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56114196A (en) * 1980-02-13 1981-09-08 Sharp Corp Ram circuit
JPS59121688A (ja) * 1982-12-28 1984-07-13 Toshiba Corp スタテイツクランダムアクセスメモリ−
US4499558A (en) * 1983-02-04 1985-02-12 General Electric Company Five-transistor static memory cell implemental in CMOS/bulk
DE3307015A1 (de) * 1983-02-28 1984-08-30 Siemens AG, 1000 Berlin und 8000 München Leseverstaerkerschaltung fuer einen statischen mos speicher
JPS61253695A (ja) * 1985-05-07 1986-11-11 Hitachi Ltd 半導体記憶装置
JPS62167698A (ja) * 1986-01-20 1987-07-24 Fujitsu Ltd 半導体記億装置
US5165039A (en) * 1986-03-28 1992-11-17 Texas Instruments Incorporated Register file for bit slice processor with simultaneous accessing of plural memory array cells
JPS62270098A (ja) * 1986-05-19 1987-11-24 Toshiba Corp 半導体センス回路
US4884240A (en) * 1986-06-19 1989-11-28 Texas Instruments Incorporated Static row driver
US4768167A (en) * 1986-09-30 1988-08-30 International Business Machines Corporation High speed CMOS latch with alternate data storage and test functions
US4949306A (en) * 1987-06-19 1990-08-14 Hitachi, Ltd. Sense circuit and semiconductor memory having a current-voltage converter circuit
JPS63316117A (ja) * 1987-06-19 1988-12-23 Fanuc Ltd 信号出力装置
GB2212681A (en) * 1987-11-20 1989-07-26 Philips Nv Accessing memory cells
JPH0323700U (ja) * 1989-07-18 1991-03-12
US5388072A (en) * 1992-04-10 1995-02-07 International Business Machines Corporation Bit line switch array for electronic computer memory
KR100365747B1 (ko) * 2000-08-31 2002-12-26 주식회사 하이닉스반도체 반도체 메모리 장치
US8077533B2 (en) * 2006-01-23 2011-12-13 Freescale Semiconductor, Inc. Memory and method for sensing data in a memory using complementary sensing scheme
US8810983B2 (en) * 2009-04-01 2014-08-19 Asco Power Technologies, L.P. Power disconnect system and method
US9875789B2 (en) * 2013-11-22 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. 3D structure for advanced SRAM design to avoid half-selected issue

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3820086A (en) * 1972-05-01 1974-06-25 Ibm Read only memory(rom)superimposed on read/write memory(ram)
US3972031A (en) * 1974-08-15 1976-07-27 Zonic Technical Laboratories, Inc. Variable length shift register alternately operable to store and recirculate data and addressing circuit therefor
US3949383A (en) * 1974-12-23 1976-04-06 Ibm Corporation D. C. Stable semiconductor memory cell

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS=1977 *

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56146964U (ja) * 1980-04-07 1981-11-05
JPS5819791A (ja) * 1981-07-27 1983-02-04 Seiko Epson Corp 半導体記憶装置
JPH0253880B2 (ja) * 1981-07-27 1990-11-20 Seiko Epson Corp
JPS6061985A (ja) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp 半導体記憶装置
JPS6061986A (ja) * 1983-09-14 1985-04-09 Mitsubishi Electric Corp 半導体記憶装置
JPH0312398B2 (ja) * 1983-09-14 1991-02-20 Mitsubishi Electric Corp
JPH0312397B2 (ja) * 1983-09-14 1991-02-20 Mitsubishi Electric Corp
JPS60119691A (ja) * 1983-11-30 1985-06-27 Nec Corp メモリ回路
JPH0330234B2 (ja) * 1983-11-30 1991-04-26
JPS60182096A (ja) * 1984-02-29 1985-09-17 Fujitsu Ltd 半導体記憶装置
JPS62103894A (ja) * 1985-10-30 1987-05-14 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 読取り完了信号発生回路

Also Published As

Publication number Publication date
DE2962765D1 (de) 1982-07-01
JPS5751192B2 (ja) 1982-10-30
EP0004444B1 (en) 1982-05-12
US4150441A (en) 1979-04-17
EP0004444A1 (en) 1979-10-03

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