JPS54134941A - Transfer system for reception character - Google Patents

Transfer system for reception character

Info

Publication number
JPS54134941A
JPS54134941A JP4298078A JP4298078A JPS54134941A JP S54134941 A JPS54134941 A JP S54134941A JP 4298078 A JP4298078 A JP 4298078A JP 4298078 A JP4298078 A JP 4298078A JP S54134941 A JPS54134941 A JP S54134941A
Authority
JP
Japan
Prior art keywords
buffer
reception
transfer
characters
character
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4298078A
Other languages
Japanese (ja)
Other versions
JPS5723286B2 (en
Inventor
Yoshiyuki Ogawa
Nobufumi Motomura
Hitoshi Toyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4298078A priority Critical patent/JPS54134941A/en
Publication of JPS54134941A publication Critical patent/JPS54134941A/en
Publication of JPS5723286B2 publication Critical patent/JPS5723286B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Data Exchanges In Wide-Area Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To obtain a communication controller with a little convergence of a load by transferring characters in a buffer and reception characters sequentially at every character reception while holding a transfer process of reception characters at the time of the reception of a read command.
CONSTITUTION: Data sent from a communication circuit in a bit-serial mode are composed and held in one-byte receiving buffer 6. When receiving a read command from a central processor, command control part 5 controls buffer counting control circuit 4 to write the contents of reception buffer 6 to transfer buffer 1 while inhibiting the transfer of received characters in reception buffer 6 and transfer buffer 1 with the capacity of several bytes to character transfer circuit 8. At every time when a character is received from a circuit after the acceptance of the read command, characters in reception buffer 6 and transfer buffer 1 are transferred to the central processor via character transfer circuit 8 in sequence.
COPYRIGHT: (C)1979,JPO&Japio
JP4298078A 1978-04-12 1978-04-12 Transfer system for reception character Granted JPS54134941A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4298078A JPS54134941A (en) 1978-04-12 1978-04-12 Transfer system for reception character

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4298078A JPS54134941A (en) 1978-04-12 1978-04-12 Transfer system for reception character

Publications (2)

Publication Number Publication Date
JPS54134941A true JPS54134941A (en) 1979-10-19
JPS5723286B2 JPS5723286B2 (en) 1982-05-18

Family

ID=12651173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4298078A Granted JPS54134941A (en) 1978-04-12 1978-04-12 Transfer system for reception character

Country Status (1)

Country Link
JP (1) JPS54134941A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49111562A (en) * 1973-02-22 1974-10-24
JPS51100653A (en) * 1975-03-04 1976-09-06 Nippon Telegraph & Telephone
JPS5255451A (en) * 1975-10-30 1977-05-06 Motorola Inc Digital device for synchronous data communication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49111562A (en) * 1973-02-22 1974-10-24
JPS51100653A (en) * 1975-03-04 1976-09-06 Nippon Telegraph & Telephone
JPS5255451A (en) * 1975-10-30 1977-05-06 Motorola Inc Digital device for synchronous data communication

Also Published As

Publication number Publication date
JPS5723286B2 (en) 1982-05-18

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