JPS54119853A - Communication control system - Google Patents

Communication control system

Info

Publication number
JPS54119853A
JPS54119853A JP2658878A JP2658878A JPS54119853A JP S54119853 A JPS54119853 A JP S54119853A JP 2658878 A JP2658878 A JP 2658878A JP 2658878 A JP2658878 A JP 2658878A JP S54119853 A JPS54119853 A JP S54119853A
Authority
JP
Japan
Prior art keywords
data
memory
frame
buffer
communication control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2658878A
Other languages
Japanese (ja)
Other versions
JPS5723889B2 (en
Inventor
Yoshinori Tsujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2658878A priority Critical patent/JPS54119853A/en
Publication of JPS54119853A publication Critical patent/JPS54119853A/en
Publication of JPS5723889B2 publication Critical patent/JPS5723889B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Computer And Data Communications (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To reduce the burden in the processor, to increase the ability of processing and to reduce the editing buffer on memory unit, by performing the detection and annulment of the short frame of reception data with communication control unit.
CONSTITUTION: When start flag pattern is received to the communication control unit 1 from the line 21, the flag detection circuit 7 resets the line 23. Succeedingly, the data received is sequentially brought to byte with the character buffer 6 and stacked to the memory 5 of the control section with sequential write-in. If defective frame is judged from the control section 3, the control section 3 throws away the stacked data in the memory 5. Further, if judged normal and the data is the control frame, then, the data in the memory 5 is transferred to the control frame buffer 8 of the memory unit 2 via the DMA transfer section 4. Further, if the data is information frame, it is fed to the information frame buffer 9 via the DMA transfer section 4.
COPYRIGHT: (C)1979,JPO&Japio
JP2658878A 1978-03-10 1978-03-10 Communication control system Granted JPS54119853A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2658878A JPS54119853A (en) 1978-03-10 1978-03-10 Communication control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2658878A JPS54119853A (en) 1978-03-10 1978-03-10 Communication control system

Publications (2)

Publication Number Publication Date
JPS54119853A true JPS54119853A (en) 1979-09-18
JPS5723889B2 JPS5723889B2 (en) 1982-05-21

Family

ID=12197694

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2658878A Granted JPS54119853A (en) 1978-03-10 1978-03-10 Communication control system

Country Status (1)

Country Link
JP (1) JPS54119853A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132242A (en) * 1974-09-13 1976-03-18 Fujitsu Ltd

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5132242A (en) * 1974-09-13 1976-03-18 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS5723889B2 (en) 1982-05-21

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