JPS54149528A - Control system for external memory for picture terminal equipment - Google Patents

Control system for external memory for picture terminal equipment

Info

Publication number
JPS54149528A
JPS54149528A JP5916178A JP5916178A JPS54149528A JP S54149528 A JPS54149528 A JP S54149528A JP 5916178 A JP5916178 A JP 5916178A JP 5916178 A JP5916178 A JP 5916178A JP S54149528 A JPS54149528 A JP S54149528A
Authority
JP
Japan
Prior art keywords
data
memory
computer
unit
terminal equipment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5916178A
Other languages
Japanese (ja)
Other versions
JPS6045458B2 (en
Inventor
Mikio Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP53059161A priority Critical patent/JPS6045458B2/en
Publication of JPS54149528A publication Critical patent/JPS54149528A/en
Publication of JPS6045458B2 publication Critical patent/JPS6045458B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Image Input (AREA)
  • Information Transfer Systems (AREA)
  • Memory System (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To extract a needed data part by transferring data required by a computer from a main memory to a buffer memory on a unit of certain width including data and by properly using both reference pulses of the computer and memory.
CONSTITUTION: The external memory used as a picture terminal equipment connected to the computer is constituted by combining a high-speed and small-capacity buffer memory and a low-speed and large-capacity main memroy. The computer performs addressing to transfer data of the unit width composed of several pieces of data from the main memory. While a data transfer pulse is effective so as to extract assigned data from unit-width data, the address of the memory is advanced by a strobed pulse and while not, on the other hand, the address is advanced by the reference pulse in the exterbal memory, thereby extracting discontinuous data continuously.
COPYRIGHT: (C)1979,JPO&Japio
JP53059161A 1978-05-17 1978-05-17 External memory control method for image terminal equipment Expired JPS6045458B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53059161A JPS6045458B2 (en) 1978-05-17 1978-05-17 External memory control method for image terminal equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53059161A JPS6045458B2 (en) 1978-05-17 1978-05-17 External memory control method for image terminal equipment

Publications (2)

Publication Number Publication Date
JPS54149528A true JPS54149528A (en) 1979-11-22
JPS6045458B2 JPS6045458B2 (en) 1985-10-09

Family

ID=13105360

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53059161A Expired JPS6045458B2 (en) 1978-05-17 1978-05-17 External memory control method for image terminal equipment

Country Status (1)

Country Link
JP (1) JPS6045458B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60182794A (en) * 1984-03-01 1985-09-18 株式会社三協精機製作所 Porcelain substrate
JPS6265399A (en) * 1985-09-17 1987-03-24 株式会社フジクラ Forming method for thick film circuit on porcelain substrate

Also Published As

Publication number Publication date
JPS6045458B2 (en) 1985-10-09

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