JPS54129936A - Communication controller - Google Patents

Communication controller

Info

Publication number
JPS54129936A
JPS54129936A JP3762478A JP3762478A JPS54129936A JP S54129936 A JPS54129936 A JP S54129936A JP 3762478 A JP3762478 A JP 3762478A JP 3762478 A JP3762478 A JP 3762478A JP S54129936 A JPS54129936 A JP S54129936A
Authority
JP
Japan
Prior art keywords
control
arithmetic controller
sio
character information
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3762478A
Other languages
Japanese (ja)
Other versions
JPS6014380B2 (en
Inventor
Yoshiaki Bandai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP53037624A priority Critical patent/JPS6014380B2/en
Publication of JPS54129936A publication Critical patent/JPS54129936A/en
Publication of JPS6014380B2 publication Critical patent/JPS6014380B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Small-Scale Networks (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE: To make it possible to offer services to several communication circuits by using the data input control part of an arithmetic controller in common among several communication controllers, by providing a control memory unit, and by attaining this assignment by an alternation switch.
CONSTITUTION: To send out character information via input-output channels SIO for series-parallel or parallel series conversion, the arithmetic controller when a transmitted machine number agrees with one of SIOs of the communication controller sets address FFAD by decoder circuit DCD and the SIO channel number is set into address register AR and stored in memory M. Through the control of control circuit CNT, the character information from the input-output bus is parallel/series- converted via corresponding SIO and then sent out. At the reception time, the information passes through the reverse path, and the output of control memory CS is selected by SW to exercise the error inspection of a control code assigned via CNT. An interruption to the arithmetic controller is made via the ANT cirucit and the arithmetic controller fetches the received character information, so that data transfer will be made between a terminal and the comupter.
COPYRIGHT: (C)1979,JPO&Japio
JP53037624A 1978-03-31 1978-03-31 Communication control device Expired JPS6014380B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53037624A JPS6014380B2 (en) 1978-03-31 1978-03-31 Communication control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53037624A JPS6014380B2 (en) 1978-03-31 1978-03-31 Communication control device

Publications (2)

Publication Number Publication Date
JPS54129936A true JPS54129936A (en) 1979-10-08
JPS6014380B2 JPS6014380B2 (en) 1985-04-12

Family

ID=12502780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53037624A Expired JPS6014380B2 (en) 1978-03-31 1978-03-31 Communication control device

Country Status (1)

Country Link
JP (1) JPS6014380B2 (en)

Also Published As

Publication number Publication date
JPS6014380B2 (en) 1985-04-12

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