SU875628A2 - Switching device - Google Patents

Description

(54) COMMUNICATED E DEVICE

one

This invention relates to automation and computing.

According to the main author. St. No 559389 A switching device is known that contains memory devices whose outputs are connected to a full switch. The full outputs of the full switch are connected to the inputs of the corresponding linear KOMMyTaTOpoBLlJ

The disadvantage of this device. is the low speed of his work due to the consistent organization of the exchange ..

The purpose of the invention is to increase the speed of action.

To this end, a switching device with K-G - bit inputs and bit outputs containing K storage devices - the bit inputs of which are device inputs, the full switch, information 1 - bits of which are connected to the corresponding outputs of the corresponding memory devices, informational T-bit outputs of a full switch are connected to the same inputs of the corresponding line switches, and 1 - bit outputs of each line switch are connected to M / K - bits outputs devices, entered decks | 1retor, register and control unit, the address outputs of memory devices are connected to the address inputs of the decoder, the output of which is connected to the register, while the first output of the control unit is connected to the control input of the decoder, and the second output is with the control input of the register, whose codes are connected to the control inputs of the line and full switches.

The drawing shows the functional, on the diagram of the switching device.

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The circuit contains inputs 1, storage devices 2, switch 3, linear switches 4, outputs 5 of the switching device, multisectional. decoder 6, register 7, control unit 8 "The device operates in a speedy manner. The input information contains the code of the output number of the switching device k to which it needs to be switched. Coming to the inputs 1 switchboard of the device information is accumulated in the memory device 2 Number codes you: soda from each storage device 2 arrive at. a multisection decoder 6, the code for its section Prosiiphire (the switched address addresses signals are stored on register 7, from which they are sent, then to the control circuits of the linear Switches 4 and the commutator 3. Control unit 8 generates two commands To the multisection decoder 6, the codes of the numbers of the outputs of the switching device are decrypted and written to the register 7. On the second command of the control unit 8, the control switching signals from the register 7 are sent to the control circuit of the switch tori 3 and 4, which carry out the switching of circuits and the parallel transmission of information from the inputs 1 of the device to the corresponding outputs of the device 5. Thus, the complete transfer of information by the switching device takes place in one cycle of operation, including 284 chaclets in itself two commands. caused by the division of the device into preparatory operations and the actual transfer of information.The introduction of the multi-section decoder 6, the register 7 and the control unit 8 allows to increase the speed of work stroystva K times. Formula of the invention. Switching device according to the author. St. No. 559389, characterized in that, in order to improve speed, a descrambler, register and control unit are entered into it, the address outputs of the memory devices are connected to the address inputs of the decoder, the output of which is connected to the register, while the first output of the control unit is connected to the control the input of the descrambler, and the second output with the control input of the register, the outputs of which are connected to the control inputs of the linear and full switches. Sources of information taken into account in the examination, 1. USSR Author's Certificate No. 559389, cl. H 03 K 17/00, 1975 (prototype).

Claims (1)

Claim The switching device according to ed. St. No. 559389, characterized in that, in order to improve performance, a decoder, a register and a control unit are introduced into it, and the address outputs of the storage devices are connected to the address inputs of a decoder, the output of which is connected to the register, while the first output of the control unit is connected to the control the decoder input, and the second output with the control input of the register, the outputs of which are connected to the control inputs of linear and full switches.