JPS54124650A - Computer - Google Patents

Computer

Info

Publication number
JPS54124650A
JPS54124650A JP3206578A JP3206578A JPS54124650A JP S54124650 A JPS54124650 A JP S54124650A JP 3206578 A JP3206578 A JP 3206578A JP 3206578 A JP3206578 A JP 3206578A JP S54124650 A JPS54124650 A JP S54124650A
Authority
JP
Japan
Prior art keywords
address
application program
limit address
contents
upper limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3206578A
Other languages
Japanese (ja)
Inventor
Iwao Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3206578A priority Critical patent/JPS54124650A/en
Publication of JPS54124650A publication Critical patent/JPS54124650A/en
Pending legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent the destruction of a basic program dependent upon the error of an application program by monitoring the next execution address and causing an interrupt to stop the execution of the application program when the application program will execute contents of an execution inhibit address set previously. CONSTITUTION:Switching circuit 132 generates a control signal stopping or operating the function of address monitor unit 13; and when this circuit is switched to the operating side, a ''1'' signal is generated to make address monitor equipment 133 operation-state, and the upper limit address and the lower limit address of the basic program stored in memory part 121 are set to register 131. Contents of sequential control counter 114 are compared with the upper limit address and the lower limit address of register 131 by address monitor equipment 133; and when contents of sequential control counter 114 have a value within the range between the upper limit address and the lower limit address, an interrupt is caused to stop the operation of an application program which generates the error.
JP3206578A 1978-03-20 1978-03-20 Computer Pending JPS54124650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3206578A JPS54124650A (en) 1978-03-20 1978-03-20 Computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3206578A JPS54124650A (en) 1978-03-20 1978-03-20 Computer

Publications (1)

Publication Number Publication Date
JPS54124650A true JPS54124650A (en) 1979-09-27

Family

ID=12348470

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3206578A Pending JPS54124650A (en) 1978-03-20 1978-03-20 Computer

Country Status (1)

Country Link
JP (1) JPS54124650A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123440U (en) * 1991-04-20 1992-11-09 日本電気アイシーマイコンシステム株式会社 micro computer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04123440U (en) * 1991-04-20 1992-11-09 日本電気アイシーマイコンシステム株式会社 micro computer

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