JPS54109339A - Shared input-output bus controller - Google Patents

Shared input-output bus controller

Info

Publication number
JPS54109339A
JPS54109339A JP1544778A JP1544778A JPS54109339A JP S54109339 A JPS54109339 A JP S54109339A JP 1544778 A JP1544778 A JP 1544778A JP 1544778 A JP1544778 A JP 1544778A JP S54109339 A JPS54109339 A JP S54109339A
Authority
JP
Japan
Prior art keywords
register
input
bank
unit
output bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1544778A
Other languages
Japanese (ja)
Other versions
JPS5913063B2 (en
Inventor
Takayuki Morioka
Takeshi Kato
Toshiyuki Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1544778A priority Critical patent/JPS5913063B2/en
Publication of JPS54109339A publication Critical patent/JPS54109339A/en
Publication of JPS5913063B2 publication Critical patent/JPS5913063B2/en
Expired legal-status Critical Current

Links

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  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE: To make it possible to extend memory addresses without changing input- output devices by providing a method, which is stored temporarily with bank numbers corresponding to input-output devices, into a shared input-output bus controller.
CONSTITUTION: Processor 1 consists of exclusive-use bus controller 13, memory unit 12 and common-use input-output bus 7, and channel controller 9D' has direct- memory-access-DMA transfer address register 14. Common-use input-output bus controllers 5 and 13 are equipped with bank registers 15 and 16. Now, when card reader 10 performs DMA transfer, bank numbers are written into corresponding parts of registers 15 and 16 and addresses are stored in register 14. Once the DMA transfer starts, the bank number equivalent to reader 10 inside of register 16 is transmitted to unit 1. At this time, unit 5 transmits a suppression signal 18 to unit 13 in order to prevent the transmission of the bank number from register 15. When the DMA device is connected to bus 3, the bank number is sent out from register 15.
COPYRIGHT: (C)1979,JPO&Japio
JP1544778A 1978-02-15 1978-02-15 Shared I/O bus controller Expired JPS5913063B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1544778A JPS5913063B2 (en) 1978-02-15 1978-02-15 Shared I/O bus controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1544778A JPS5913063B2 (en) 1978-02-15 1978-02-15 Shared I/O bus controller

Publications (2)

Publication Number Publication Date
JPS54109339A true JPS54109339A (en) 1979-08-27
JPS5913063B2 JPS5913063B2 (en) 1984-03-27

Family

ID=11889053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1544778A Expired JPS5913063B2 (en) 1978-02-15 1978-02-15 Shared I/O bus controller

Country Status (1)

Country Link
JP (1) JPS5913063B2 (en)

Also Published As

Publication number Publication date
JPS5913063B2 (en) 1984-03-27

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