JPS54102939A - Timer circuit - Google Patents

Timer circuit

Info

Publication number
JPS54102939A
JPS54102939A JP950278A JP950278A JPS54102939A JP S54102939 A JPS54102939 A JP S54102939A JP 950278 A JP950278 A JP 950278A JP 950278 A JP950278 A JP 950278A JP S54102939 A JPS54102939 A JP S54102939A
Authority
JP
Japan
Prior art keywords
counter
timer
value
counts
oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP950278A
Other languages
Japanese (ja)
Other versions
JPS5835288B2 (en
Inventor
Ichiro Nakajima
Masahiro Kuriyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53009502A priority Critical patent/JPS5835288B2/en
Publication of JPS54102939A publication Critical patent/JPS54102939A/en
Publication of JPS5835288B2 publication Critical patent/JPS5835288B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE: To obtain a high-accuracy timer circuit by providing the counter which counts the output signals of the oscillator up to the prescribed value and then grows the timer renewal start signals plus the counter which counts the timer renewal start signals in the prescribed frequencies.
CONSTITUTION: The pulse sent from oscillator 1 is converted into 2μs pulse via 4-step division 2 and differentiation 3 to advance 8-bit binary counter 4, Counter 4 is set to original value decimal 88 with counter 6 set to 01. When the count value of counter 4 reaches 255, the carry is given to renew the timer. Counter 6 changes to 10, and the lowest bit of counter 4 is set to the value of counter 6 before alteration to start counting again at 88 and then to generate the carry at 255. Counter 6 changes to 00, and the lowest bit of counter 4 is set to 1 before alteration of counter 6 to start counting from 89. Thus, the timer renewal period becomes 334μs twice in 3 times and becomes 332μs once with no accumulation of error.
COPYRIGHT: (C)1979,JPO&Japio
JP53009502A 1978-01-31 1978-01-31 timer circuit Expired JPS5835288B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53009502A JPS5835288B2 (en) 1978-01-31 1978-01-31 timer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53009502A JPS5835288B2 (en) 1978-01-31 1978-01-31 timer circuit

Publications (2)

Publication Number Publication Date
JPS54102939A true JPS54102939A (en) 1979-08-13
JPS5835288B2 JPS5835288B2 (en) 1983-08-02

Family

ID=11722007

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53009502A Expired JPS5835288B2 (en) 1978-01-31 1978-01-31 timer circuit

Country Status (1)

Country Link
JP (1) JPS5835288B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04105481U (en) * 1991-02-25 1992-09-10 国際電気株式会社 Connector for wiring connection

Also Published As

Publication number Publication date
JPS5835288B2 (en) 1983-08-02

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