JPS57154944A - Retriggerable frequency divider - Google Patents

Retriggerable frequency divider

Info

Publication number
JPS57154944A
JPS57154944A JP3959281A JP3959281A JPS57154944A JP S57154944 A JPS57154944 A JP S57154944A JP 3959281 A JP3959281 A JP 3959281A JP 3959281 A JP3959281 A JP 3959281A JP S57154944 A JPS57154944 A JP S57154944A
Authority
JP
Japan
Prior art keywords
counter
trigger signal
flop
flip
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3959281A
Other languages
Japanese (ja)
Inventor
Seiji Kinoshita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3959281A priority Critical patent/JPS57154944A/en
Publication of JPS57154944A publication Critical patent/JPS57154944A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/38—Starting, stopping or resetting the counter

Landscapes

  • Accommodation For Nursing Or Treatment Tables (AREA)

Abstract

PURPOSE:To ensure the restarting after resetting a counter enven while the counting is kept on, by delivering the reset signal to the counter just for a half period of the clock when a trigger signal is supplied. CONSTITUTION:An n-stage binary counter 2 is initialized when it counts m units of clocks and then start the counting again. When the 1st trigger signal is supplied, the output Q of a flip-flop 1 is set at ''1''. Thus the reset mode is released for the counter 2 and a flip-flop 4. After this, the trigger signal can be accepted. With application of the 2nd trigger signal, the output Q of the flip-flop 4 is switched to ''1'' from ''0''. As a result, the logic value ''1'' is supplied to the reset terminal of the counter 2 via an OR circuit 8. Thus the counter 2 counts the clock pulses again from the beginning.
JP3959281A 1981-03-20 1981-03-20 Retriggerable frequency divider Pending JPS57154944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3959281A JPS57154944A (en) 1981-03-20 1981-03-20 Retriggerable frequency divider

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3959281A JPS57154944A (en) 1981-03-20 1981-03-20 Retriggerable frequency divider

Publications (1)

Publication Number Publication Date
JPS57154944A true JPS57154944A (en) 1982-09-24

Family

ID=12557370

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3959281A Pending JPS57154944A (en) 1981-03-20 1981-03-20 Retriggerable frequency divider

Country Status (1)

Country Link
JP (1) JPS57154944A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62200912A (en) * 1986-02-28 1987-09-04 Oki Electric Ind Co Ltd Timing generation circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62200912A (en) * 1986-02-28 1987-09-04 Oki Electric Ind Co Ltd Timing generation circuit

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