JPS5623027A - Timer unit of external trigger type - Google Patents

Timer unit of external trigger type

Info

Publication number
JPS5623027A
JPS5623027A JP9843479A JP9843479A JPS5623027A JP S5623027 A JPS5623027 A JP S5623027A JP 9843479 A JP9843479 A JP 9843479A JP 9843479 A JP9843479 A JP 9843479A JP S5623027 A JPS5623027 A JP S5623027A
Authority
JP
Japan
Prior art keywords
flip flop
output
level
reset terminal
time limit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9843479A
Other languages
Japanese (ja)
Inventor
Aritaka Yorifuji
Kenichi Yoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP9843479A priority Critical patent/JPS5623027A/en
Publication of JPS5623027A publication Critical patent/JPS5623027A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching

Landscapes

  • Electronic Switches (AREA)

Abstract

PURPOSE:To prevent the inconvenience that the time limit output is made regardless that no time limit trigger signal is fed, by providing the delay circuit holding the reset terminal of RS flip flop at H level for a given time immediately after the application of power supply. CONSTITUTION:The time limit trigger signal is input to the set terminal S of the RS flip flop F, the clock pulse of the oscillation section 1 is counted at the counter 2, and the output is input to the reset terminal R of the flip flop F. When RS both inputs are at H level, the lacth circuit 6 is provided so that the output Q' of the flip flop F can be held at L level, and the operation of the counter 2 is controlled via the control section 3 with the output of the flip flop F and the delay circuit 7 to hold the reset terminal R of the flip flop F for a given time after the application of power supply is provided.
JP9843479A 1979-07-31 1979-07-31 Timer unit of external trigger type Pending JPS5623027A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9843479A JPS5623027A (en) 1979-07-31 1979-07-31 Timer unit of external trigger type

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9843479A JPS5623027A (en) 1979-07-31 1979-07-31 Timer unit of external trigger type

Publications (1)

Publication Number Publication Date
JPS5623027A true JPS5623027A (en) 1981-03-04

Family

ID=14219683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9843479A Pending JPS5623027A (en) 1979-07-31 1979-07-31 Timer unit of external trigger type

Country Status (1)

Country Link
JP (1) JPS5623027A (en)

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