JPS54100202A - Automatic channel selection device for receiving unit - Google Patents
Automatic channel selection device for receiving unitInfo
- Publication number
- JPS54100202A JPS54100202A JP684978A JP684978A JPS54100202A JP S54100202 A JPS54100202 A JP S54100202A JP 684978 A JP684978 A JP 684978A JP 684978 A JP684978 A JP 684978A JP S54100202 A JPS54100202 A JP S54100202A
- Authority
- JP
- Japan
- Prior art keywords
- clock input
- input terminal
- level
- signal
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To prevent the malfunction in an assured way for the 1-step operation of the synthesizer tuner or the like by inserting the delay circuit and the edge detector circuit between the output sides of the 1st and 2nd switches for 1-step operation and the clock input terminal of the 1st-step decimal counter.
CONSTITUTION: Decimal counters 41∼43 in which both the digit-up and digit- down output are delivered through the carry-out terminal are connected to logic gate 45 and 46. Gate 45 and 46 give the signal level to the clock input terminal of the rear step side counter only when a coincidence is obtained between the level to be applied to the clock input terminal of the front step side counter along with the level of the carry-out terminal and the counting pre-level of the rear step side counter. Then the signal is delayed via delay circuit 60 and 61 inserted between the clock input terminal of the 1st step decimal counter and the signal output side of 1-step operation switch S1' and S2', and the start point of the signal is detected through edge detector circuit 58 to generate the short pulse. Thus, the malfunction can be prevented assuredly for the 1-step operation of the synthesizer tuner and others.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP684978A JPS54100202A (en) | 1978-01-25 | 1978-01-25 | Automatic channel selection device for receiving unit |
US05/973,631 US4245349A (en) | 1977-12-29 | 1978-12-27 | Automatic frequency scanning radio receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP684978A JPS54100202A (en) | 1978-01-25 | 1978-01-25 | Automatic channel selection device for receiving unit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS54100202A true JPS54100202A (en) | 1979-08-07 |
JPS5756973B2 JPS5756973B2 (en) | 1982-12-02 |
Family
ID=11649677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP684978A Granted JPS54100202A (en) | 1977-12-29 | 1978-01-25 | Automatic channel selection device for receiving unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54100202A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7493915B2 (en) | 2003-09-17 | 2009-02-24 | Lg Electronics Inc. | Discharge valve for compressor |
JP2017034622A (en) * | 2015-08-06 | 2017-02-09 | アズビル株式会社 | Pulse output device |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6271271U (en) * | 1985-10-25 | 1987-05-07 |
-
1978
- 1978-01-25 JP JP684978A patent/JPS54100202A/en active Granted
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7493915B2 (en) | 2003-09-17 | 2009-02-24 | Lg Electronics Inc. | Discharge valve for compressor |
JP2017034622A (en) * | 2015-08-06 | 2017-02-09 | アズビル株式会社 | Pulse output device |
Also Published As
Publication number | Publication date |
---|---|
JPS5756973B2 (en) | 1982-12-02 |
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