JPS5363978A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5363978A
JPS5363978A JP14002076A JP14002076A JPS5363978A JP S5363978 A JPS5363978 A JP S5363978A JP 14002076 A JP14002076 A JP 14002076A JP 14002076 A JP14002076 A JP 14002076A JP S5363978 A JPS5363978 A JP S5363978A
Authority
JP
Japan
Prior art keywords
semiconductor device
pads
avert
equalize
temperatures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14002076A
Other languages
Japanese (ja)
Inventor
Matsuzo Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14002076A priority Critical patent/JPS5363978A/en
Publication of JPS5363978A publication Critical patent/JPS5363978A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10125Reinforcing structures
    • H01L2224/10126Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: To avert the concentration of large current only at the junctions near pads and equalize the temperatures on chip surface by positioning the bonding pads on the semiconductor chip near the side closes to an outside mounting heat sink.
COPYRIGHT: (C)1978,JPO&Japio
JP14002076A 1976-11-19 1976-11-19 Semiconductor device Pending JPS5363978A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14002076A JPS5363978A (en) 1976-11-19 1976-11-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14002076A JPS5363978A (en) 1976-11-19 1976-11-19 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5363978A true JPS5363978A (en) 1978-06-07

Family

ID=15259063

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14002076A Pending JPS5363978A (en) 1976-11-19 1976-11-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5363978A (en)

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