JPS5355972A - Engagement method and electronic device using said method - Google Patents

Engagement method and electronic device using said method

Info

Publication number
JPS5355972A
JPS5355972A JP13104476A JP13104476A JPS5355972A JP S5355972 A JPS5355972 A JP S5355972A JP 13104476 A JP13104476 A JP 13104476A JP 13104476 A JP13104476 A JP 13104476A JP S5355972 A JPS5355972 A JP S5355972A
Authority
JP
Japan
Prior art keywords
electronic device
engagement
simplify
secure
press
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13104476A
Other languages
Japanese (ja)
Inventor
Kanemitsu Kubota
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Epson Corp
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK, Epson Corp filed Critical Seiko Epson Corp
Priority to JP13104476A priority Critical patent/JPS5355972A/en
Publication of JPS5355972A publication Critical patent/JPS5355972A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To press an IC ship onto the lead frame via a conductive anisotropic elastic substance in order to secure an electric conduction between them,and thus to simplify the junction method.
COPYRIGHT: (C)1978,JPO&Japio
JP13104476A 1976-10-29 1976-10-29 Engagement method and electronic device using said method Pending JPS5355972A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13104476A JPS5355972A (en) 1976-10-29 1976-10-29 Engagement method and electronic device using said method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13104476A JPS5355972A (en) 1976-10-29 1976-10-29 Engagement method and electronic device using said method

Publications (1)

Publication Number Publication Date
JPS5355972A true JPS5355972A (en) 1978-05-20

Family

ID=15048695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13104476A Pending JPS5355972A (en) 1976-10-29 1976-10-29 Engagement method and electronic device using said method

Country Status (1)

Country Link
JP (1) JPS5355972A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0279451A (en) * 1988-09-14 1990-03-20 Hitachi Ltd Semiconductor device, its cooling and manufacturing methods

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0279451A (en) * 1988-09-14 1990-03-20 Hitachi Ltd Semiconductor device, its cooling and manufacturing methods

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