JPS5334466A - Electrode construction of semiconductor device - Google Patents

Electrode construction of semiconductor device

Info

Publication number
JPS5334466A
JPS5334466A JP10923476A JP10923476A JPS5334466A JP S5334466 A JPS5334466 A JP S5334466A JP 10923476 A JP10923476 A JP 10923476A JP 10923476 A JP10923476 A JP 10923476A JP S5334466 A JPS5334466 A JP S5334466A
Authority
JP
Japan
Prior art keywords
semiconductor device
electrode construction
distortion
bonding
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10923476A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5726410B2 (en:Method
Inventor
Masanobu Obara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10923476A priority Critical patent/JPS5334466A/ja
Publication of JPS5334466A publication Critical patent/JPS5334466A/ja
Publication of JPS5726410B2 publication Critical patent/JPS5726410B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP10923476A 1976-09-10 1976-09-10 Electrode construction of semiconductor device Granted JPS5334466A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10923476A JPS5334466A (en) 1976-09-10 1976-09-10 Electrode construction of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10923476A JPS5334466A (en) 1976-09-10 1976-09-10 Electrode construction of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5334466A true JPS5334466A (en) 1978-03-31
JPS5726410B2 JPS5726410B2 (en:Method) 1982-06-04

Family

ID=14505006

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10923476A Granted JPS5334466A (en) 1976-09-10 1976-09-10 Electrode construction of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5334466A (en:Method)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61289652A (ja) * 1985-06-18 1986-12-19 Oki Electric Ind Co Ltd 半導体装置
JPS6219741U (en:Method) * 1985-07-20 1987-02-05
JP2003510815A (ja) * 1999-09-20 2003-03-18 テレフオンアクチーボラゲット エル エム エリクソン（パブル） 能動素子上に設けられた接着パッドを備える半導体チップ

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61289652A (ja) * 1985-06-18 1986-12-19 Oki Electric Ind Co Ltd 半導体装置
JPS6219741U (en:Method) * 1985-07-20 1987-02-05
JP2003510815A (ja) * 1999-09-20 2003-03-18 テレフオンアクチーボラゲット エル エム エリクソン（パブル） 能動素子上に設けられた接着パッドを備える半導体チップ

Also Published As

Publication number Publication date
JPS5726410B2 (en:Method) 1982-06-04

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