JPS5329551B2 - - Google Patents

Info

Publication number
JPS5329551B2
JPS5329551B2 JP9418374A JP9418374A JPS5329551B2 JP S5329551 B2 JPS5329551 B2 JP S5329551B2 JP 9418374 A JP9418374 A JP 9418374A JP 9418374 A JP9418374 A JP 9418374A JP S5329551 B2 JPS5329551 B2 JP S5329551B2
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP9418374A
Other languages
Japanese (ja)
Other versions
JPS5121793A (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9418374A priority Critical patent/JPS5329551B2/ja
Priority to US05/604,947 priority patent/US4017341A/en
Priority to CA233,654A priority patent/CA1039856A/en
Priority to AU84183/75A priority patent/AU476940B2/en
Publication of JPS5121793A publication Critical patent/JPS5121793A/ja
Publication of JPS5329551B2 publication Critical patent/JPS5329551B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/12—Diffusion of dopants within, into or out of semiconductor bodies or layers between a solid phase and a gaseous phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/021—Manufacture or treatment of air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/20—Air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/003—Anneal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/118—Oxide films
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline

Landscapes

  • Element Separation (AREA)
JP9418374A 1974-08-19 1974-08-19 Expired JPS5329551B2 (https=)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9418374A JPS5329551B2 (https=) 1974-08-19 1974-08-19
US05/604,947 US4017341A (en) 1974-08-19 1975-08-15 Method of manufacturing semiconductor integrated circuit with prevention of substrate warpage
CA233,654A CA1039856A (en) 1974-08-19 1975-08-18 Method of manufacturing semiconductor integrated circuit
AU84183/75A AU476940B2 (en) 1974-08-19 1975-08-21 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9418374A JPS5329551B2 (https=) 1974-08-19 1974-08-19

Publications (2)

Publication Number Publication Date
JPS5121793A JPS5121793A (https=) 1976-02-21
JPS5329551B2 true JPS5329551B2 (https=) 1978-08-22

Family

ID=14103193

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9418374A Expired JPS5329551B2 (https=) 1974-08-19 1974-08-19

Country Status (4)

Country Link
US (1) US4017341A (https=)
JP (1) JPS5329551B2 (https=)
AU (1) AU476940B2 (https=)
CA (1) CA1039856A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6091379U (ja) * 1983-06-30 1985-06-22 田辺金属株式会社 包丁ハンドルの固着装置

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4173674A (en) * 1975-05-12 1979-11-06 Hitachi, Ltd. Dielectric insulator separated substrate for semiconductor integrated circuits
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
JPS55138229A (en) * 1979-04-13 1980-10-28 Hitachi Ltd Manufacture of dielectric material for insulation- separation substrate
US4292730A (en) * 1980-03-12 1981-10-06 Harris Corporation Method of fabricating mesa bipolar memory cell utilizing epitaxial deposition, substrate removal and special metallization
US4404658A (en) * 1980-03-12 1983-09-13 Harris Corporation Mesa bipolar memory cell and method of fabrication
US4372803A (en) * 1980-09-26 1983-02-08 The United States Of America As Represented By The Secretary Of The Navy Method for etch thinning silicon devices
US4408386A (en) * 1980-12-12 1983-10-11 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor integrated circuit devices
US4411060A (en) * 1981-07-06 1983-10-25 Western Electric Co., Inc. Method of manufacturing dielectrically-isolated single-crystal semiconductor substrates
US4501060A (en) * 1983-01-24 1985-02-26 At&T Bell Laboratories Dielectrically isolated semiconductor devices
US4571818A (en) * 1983-09-29 1986-02-25 At&T Bell Laboratories Isolation process for high-voltage semiconductor devices
JPS6080264A (ja) * 1983-10-07 1985-05-08 Toshiba Corp 半導体装置
JPS6173345A (ja) * 1984-09-19 1986-04-15 Toshiba Corp 半導体装置
US4581814A (en) * 1984-12-13 1986-04-15 At&T Bell Laboratories Process for fabricating dielectrically isolated devices utilizing heating of the polycrystalline support layer to prevent substrate deformation
US4716447A (en) * 1985-09-20 1987-12-29 Rca Corporation Interrupting charge integration in semiconductor imagers exposed to radiant energy
US4875086A (en) * 1987-05-22 1989-10-17 Texas Instruments Incorporated Silicon-on-insulator integrated circuits and method
JPS6457207A (en) * 1987-08-28 1989-03-03 Hitachi Ltd Waveguide type optical device
US4870029A (en) * 1987-10-09 1989-09-26 American Telephone And Telegraph Company, At&T-Technologies, Inc. Method of forming complementary device structures in partially processed dielectrically isolated wafers
US4784970A (en) * 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor
JPH0355822A (ja) * 1989-07-25 1991-03-11 Shin Etsu Handotai Co Ltd 半導体素子形成用基板の製造方法
JPH0636414B2 (ja) * 1989-08-17 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JPH03129854A (ja) * 1989-10-16 1991-06-03 Toshiba Corp 半導体装置の製造方法
US5034343A (en) * 1990-03-08 1991-07-23 Harris Corporation Manufacturing ultra-thin wafer using a handle wafer
JPH046875A (ja) * 1990-04-24 1992-01-10 Mitsubishi Materials Corp シリコンウェーハ
JPH07118505B2 (ja) * 1990-12-28 1995-12-18 信越半導体株式会社 誘電体分離基板の製造方法
US5382551A (en) * 1993-04-09 1995-01-17 Micron Semiconductor, Inc. Method for reducing the effects of semiconductor substrate deformities
JPH08274285A (ja) * 1995-03-29 1996-10-18 Komatsu Electron Metals Co Ltd Ｓｏｉ基板及びその製造方法
JPH11505671A (ja) * 1996-03-12 1999-05-21 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ ハイブリッド集積回路の製造方法
US6198114B1 (en) * 1997-10-28 2001-03-06 Stmicroelectronics, Inc. Field effect transistor having dielectrically isolated sources and drains and method for making same
JP4232605B2 (ja) 2003-10-30 2009-03-04 住友電気工業株式会社 窒化物半導体基板の製造方法と窒化物半導体基板
SG148895A1 (en) * 2007-07-04 2009-01-29 Tinggi Technologies Private Ltd Separation of semiconductor devices for light emission
US8809202B2 (en) * 2012-02-14 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices including use of a protective material

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1514818A1 (de) * 1951-01-28 1969-05-08 Telefunken Patent Festkoerperschaltung,bestehend aus einem Halbleiterkoerper mit eingebrachten aktiven Bauelementen und einer Isolierschicht mit aufgebrachten passiven Bauelementen und Leitungsbahnen
US3381182A (en) * 1964-10-19 1968-04-30 Philco Ford Corp Microcircuits having buried conductive layers
US3494809A (en) * 1967-06-05 1970-02-10 Honeywell Inc Semiconductor processing
US3566220A (en) * 1969-04-25 1971-02-23 Texas Instruments Inc Integrated semiconductor circuit having complementary transistors provided with dielectric isolation and surface collector contacts
US3721588A (en) * 1971-08-13 1973-03-20 Motorola Inc Thin single crystal silicon on an insulating substrate and improved dielectric isolation processing method
US3798753A (en) * 1971-11-12 1974-03-26 Signetics Corp Method for making bulk resistor and integrated circuit using the same
JPS5134268B2 (https=) * 1972-07-13 1976-09-25
US3929528A (en) * 1973-01-12 1975-12-30 Motorola Inc Fabrication of monocriptalline silicon on insulating substrates utilizing selective etching and deposition techniques
US3862852A (en) * 1973-06-01 1975-01-28 Fairchild Camera Instr Co Method of obtaining high-quality thick films of polycrystalline silicone from dielectric isolation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6091379U (ja) * 1983-06-30 1985-06-22 田辺金属株式会社 包丁ハンドルの固着装置

Also Published As

Publication number Publication date
US4017341A (en) 1977-04-12
JPS5121793A (https=) 1976-02-21
AU8418375A (en) 1976-10-07
CA1039856A (en) 1978-10-03
AU476940B2 (en) 1976-10-07

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