JPS5321569A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5321569A
JPS5321569A JP9651776A JP9651776A JPS5321569A JP S5321569 A JPS5321569 A JP S5321569A JP 9651776 A JP9651776 A JP 9651776A JP 9651776 A JP9651776 A JP 9651776A JP S5321569 A JPS5321569 A JP S5321569A
Authority
JP
Japan
Prior art keywords
production
semiconductor device
smoothing
disconnection
prevent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9651776A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5712536B2 (ref
Inventor
Masaharu Noyori
Hiroaki Fujimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9651776A priority Critical patent/JPS5321569A/ja
Publication of JPS5321569A publication Critical patent/JPS5321569A/ja
Publication of JPS5712536B2 publication Critical patent/JPS5712536B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Wire Bonding (AREA)
JP9651776A 1976-08-11 1976-08-11 Production of semiconductor device Granted JPS5321569A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9651776A JPS5321569A (en) 1976-08-11 1976-08-11 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9651776A JPS5321569A (en) 1976-08-11 1976-08-11 Production of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5321569A true JPS5321569A (en) 1978-02-28
JPS5712536B2 JPS5712536B2 (ref) 1982-03-11

Family

ID=14167321

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9651776A Granted JPS5321569A (en) 1976-08-11 1976-08-11 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5321569A (ref)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117476A (ja) * 2007-11-02 2009-05-28 Seiko Epson Corp 電子部品の実装構造
US11718182B2 (en) 2020-01-02 2023-08-08 Crrc Qingdao Sifang Co., Ltd. Railway vehicle with aerodynamic lift control device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009117476A (ja) * 2007-11-02 2009-05-28 Seiko Epson Corp 電子部品の実装構造
US8227914B2 (en) 2007-11-02 2012-07-24 Seiko Epson Corporation Mounting structure of electronic component
US11718182B2 (en) 2020-01-02 2023-08-08 Crrc Qingdao Sifang Co., Ltd. Railway vehicle with aerodynamic lift control device

Also Published As

Publication number Publication date
JPS5712536B2 (ref) 1982-03-11

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