JPS5310969A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5310969A
JPS5310969A JP8512976A JP8512976A JPS5310969A JP S5310969 A JPS5310969 A JP S5310969A JP 8512976 A JP8512976 A JP 8512976A JP 8512976 A JP8512976 A JP 8512976A JP S5310969 A JPS5310969 A JP S5310969A
Authority
JP
Japan
Prior art keywords
production
semiconductor device
chip
lapping
depositing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8512976A
Other languages
Japanese (ja)
Inventor
Masao Tsuruoka
Takayuki Wakui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8512976A priority Critical patent/JPS5310969A/en
Publication of JPS5310969A publication Critical patent/JPS5310969A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE: To prevent the increase in contact resistance by depositing the same conductivity type layer of a high impurity concentration on the main surface of a chip, fitting the chip into a glass layer and lapping the surface.
COPYRIGHT: (C)1978,JPO&Japio
JP8512976A 1976-07-19 1976-07-19 Production of semiconductor device Pending JPS5310969A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8512976A JPS5310969A (en) 1976-07-19 1976-07-19 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8512976A JPS5310969A (en) 1976-07-19 1976-07-19 Production of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5310969A true JPS5310969A (en) 1978-01-31

Family

ID=13850031

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8512976A Pending JPS5310969A (en) 1976-07-19 1976-07-19 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5310969A (en)

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