JPS52124878A - Production of semiconductor integrated circuit - Google Patents
Production of semiconductor integrated circuitInfo
- Publication number
- JPS52124878A JPS52124878A JP4089476A JP4089476A JPS52124878A JP S52124878 A JPS52124878 A JP S52124878A JP 4089476 A JP4089476 A JP 4089476A JP 4089476 A JP4089476 A JP 4089476A JP S52124878 A JPS52124878 A JP S52124878A
- Authority
- JP
- Japan
- Prior art keywords
- production
- integrated circuit
- semiconductor integrated
- thyristors
- ics
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 230000010354 integration Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/7436—Lateral thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Element Separation (AREA)
Abstract
PURPOSE:To increase the scale of integration of ICs of thyristors, etc. by forming isolating grooves from the top and bottom surfaces of a semiconductor substrate to make dielectric isolation structure.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4089476A JPS52124878A (en) | 1976-04-13 | 1976-04-13 | Production of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4089476A JPS52124878A (en) | 1976-04-13 | 1976-04-13 | Production of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS52124878A true JPS52124878A (en) | 1977-10-20 |
Family
ID=12593206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4089476A Pending JPS52124878A (en) | 1976-04-13 | 1976-04-13 | Production of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS52124878A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4941956A (en) * | 1972-05-01 | 1974-04-19 | ||
US3969749A (en) * | 1974-04-01 | 1976-07-13 | Texas Instruments Incorporated | Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide |
-
1976
- 1976-04-13 JP JP4089476A patent/JPS52124878A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4941956A (en) * | 1972-05-01 | 1974-04-19 | ||
US3969749A (en) * | 1974-04-01 | 1976-07-13 | Texas Instruments Incorporated | Substrate for dielectric isolated integrated circuit with V-etched depth grooves for lapping guide |
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