JPS4935029B1 - - Google Patents

Info

Publication number
JPS4935029B1
JPS4935029B1 JP45113205A JP11320570A JPS4935029B1 JP S4935029 B1 JPS4935029 B1 JP S4935029B1 JP 45113205 A JP45113205 A JP 45113205A JP 11320570 A JP11320570 A JP 11320570A JP S4935029 B1 JPS4935029 B1 JP S4935029B1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP45113205A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPS4935029B1 publication Critical patent/JPS4935029B1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/019—Manufacture or treatment of isolation regions comprising dielectric materials using epitaxial passivated integrated circuit [EPIC] processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/40—Encapsulations, e.g. protective coatings characterised by their materials
    • H10W74/43—Encapsulations, e.g. protective coatings characterised by their materials comprising oxides, nitrides or carbides, e.g. ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/043—Dual dielectric
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/114—Nitrides of silicon
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/122—Polycrystalline
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/95—Multilayer mask including nonradiation sensitive layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]

Landscapes

  • Element Separation (AREA)
  • Optical Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
JP45113205A 1970-01-06 1970-12-18 Pending JPS4935029B1 (enExample)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88370A 1970-01-06 1970-01-06

Publications (1)

Publication Number Publication Date
JPS4935029B1 true JPS4935029B1 (enExample) 1974-09-19

Family

ID=21693426

Family Applications (1)

Application Number Title Priority Date Filing Date
JP45113205A Pending JPS4935029B1 (enExample) 1970-01-06 1970-12-18

Country Status (5)

Country Link
US (1) US3666548A (enExample)
JP (1) JPS4935029B1 (enExample)
DE (1) DE2046833C3 (enExample)
FR (1) FR2075939B1 (enExample)
GB (1) GB1274726A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887143A (en) * 1988-03-28 1989-12-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Families Citing this family (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4946800A (en) * 1965-09-28 1990-08-07 Li Chou H Method for making solid-state device utilizing isolation grooves
US3903324A (en) * 1969-12-30 1975-09-02 Ibm Method of changing the physical properties of a metallic film by ion beam formation
GB1334520A (en) * 1970-06-12 1973-10-17 Atomic Energy Authority Uk Formation of electrically insulating layers in semiconducting materials
US3897274A (en) * 1971-06-01 1975-07-29 Texas Instruments Inc Method of fabricating dielectrically isolated semiconductor structures
DE2155849C3 (de) * 1971-11-10 1979-07-26 Semikron Gesellschaft Fuer Gleichrichterbau Und Elektronik Mbh, 8500 Nuernberg Verfahren zur Herstellung eines stabilisierenden und/oder isolierenden Überzuges auf Halbleiteroberflächen
JPS519269B2 (enExample) * 1972-05-19 1976-03-25
US3873373A (en) * 1972-07-06 1975-03-25 Bryan H Hill Fabrication of a semiconductor device
US3983264A (en) * 1972-07-20 1976-09-28 Texas Instruments Incorporated Metal-semiconductor ohmic contacts and methods of fabrication
DE2235865A1 (de) * 1972-07-21 1974-01-31 Licentia Gmbh Halbleiteranordnung aus einer vielzahl von in einem gemeinsamen halbleiterkoerper untergebrachten halbleiterbauelementen
US4017887A (en) * 1972-07-25 1977-04-12 The United States Of America As Represented By The Secretary Of The Air Force Method and means for passivation and isolation in semiconductor devices
US4015893A (en) * 1972-10-12 1977-04-05 Kentaro Hayashi, President, University of Tokyo Compound semiconductor optical integrated circuit having isolation zones for light transmission
US3897273A (en) * 1972-11-06 1975-07-29 Hughes Aircraft Co Process for forming electrically isolating high resistivity regions in GaAs
US3860454A (en) * 1973-06-27 1975-01-14 Ibm Field effect transistor structure for minimizing parasitic inversion and process for fabricating
US3845496A (en) * 1973-09-10 1974-10-29 Rca Corp Infrared photocathode
US3855009A (en) * 1973-09-20 1974-12-17 Texas Instruments Inc Ion-implantation and conventional epitaxy to produce dielectrically isolated silicon layers
US3938176A (en) * 1973-09-24 1976-02-10 Texas Instruments Incorporated Process for fabricating dielectrically isolated semiconductor components of an integrated circuit
US3943555A (en) * 1974-05-02 1976-03-09 Rca Corporation SOS Bipolar transistor
JPS5329555B2 (enExample) * 1974-11-22 1978-08-22
DE2507366C3 (de) * 1975-02-20 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Unterdrückung parasitärer Schaltungselemente
JPS5197385A (en) * 1975-02-21 1976-08-26 Handotaisochino seizohoho
US3994012A (en) * 1975-05-07 1976-11-23 The Regents Of The University Of Minnesota Photovoltaic semi-conductor devices
NL7513161A (nl) * 1975-11-11 1977-05-13 Philips Nv Werkwijze ter vervaardiging van een halfgeleider- inrichting, en inrichting vervaardigd volgens de werkwijze.
DE2553685C2 (de) * 1975-11-28 1985-05-09 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Herstellung eines optischen Richtkopplers
DD136670A1 (de) * 1976-02-04 1979-07-18 Rudolf Sacher Verfahren und vorrichtung zur herstellung von halbleiterstrukturen
US4105805A (en) * 1976-12-29 1978-08-08 The United States Of America As Represented By The Secretary Of The Army Formation of metal nitride oxide semiconductor (MNOS) by ion implantation of oxygen through a silicon nitride layer
NL7701559A (nl) * 1977-02-15 1978-08-17 Philips Nv Het maken van schuine hellingen aan metaal- patronen, alsmede substraat voor een geinte- greerde schakeling voorzien van een dergelijk patroon.
JPS5721856B2 (en) * 1977-11-28 1982-05-10 Nippon Telegraph & Telephone Semiconductor and its manufacture
US4262056A (en) * 1978-09-15 1981-04-14 The United States Of America As Represented By The Secretary Of The Navy Ion-implanted multilayer optical interference filter
GB2038548B (en) * 1978-10-27 1983-03-23 Nippon Telegraph & Telephone Isolating semiconductor device by porous silicon oxide
US4262299A (en) * 1979-01-29 1981-04-14 Rca Corporation Semiconductor-on-insulator device and method for its manufacture
JPS6059994B2 (ja) * 1979-10-09 1985-12-27 三菱電機株式会社 アルミニウム膜またはアルミニウム合金膜の微細パタ−ン形成方法
GB2085224B (en) * 1980-10-07 1984-08-15 Itt Ind Ltd Isolating sc device using oxygen duping
US4450041A (en) * 1982-06-21 1984-05-22 The United States Of America As Represented By The Secretary Of The Navy Chemical etching of transformed structures
US4542009A (en) * 1983-04-21 1985-09-17 Combustion Engineering, Inc. Synthesis of intercalatable layered stable transition metal chalcogenides and alkali metal-transition metal chalcogenides
NL8303905A (nl) * 1983-11-15 1985-06-03 Philips Nv Werkwijze voor het vervaardigen van een geodetische component en geintegreerde optische inrichting die deze component bevat.
US4579626A (en) * 1985-02-28 1986-04-01 Rca Corporation Method of making a charge-coupled device imager
JPS6281745A (ja) * 1985-10-05 1987-04-15 Fujitsu Ltd ウエハ−規模のｌｓｉ半導体装置とその製造方法
GB2210728B (en) * 1987-10-07 1991-11-13 Stc Plc Isolation trenches for semiconductors
US5602403A (en) * 1991-03-01 1997-02-11 The United States Of America As Represented By The Secretary Of The Navy Ion Implantation buried gate insulator field effect transistor
US5895252A (en) * 1994-05-06 1999-04-20 United Microelectronics Corporation Field oxidation by implanted oxygen (FIMOX)
US7825488B2 (en) 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
CN102270598B (zh) * 2011-08-19 2013-08-14 北京大学 一种用于集成电路制造的场区隔离方法
CN102270599A (zh) * 2011-08-22 2011-12-07 北京大学 一种用于集成电路制造的场区隔离方法
CN118156343B (zh) * 2024-05-10 2024-09-13 金阳(泉州)新能源科技有限公司 一种大幅降低漏电的背接触电池及其制作方法和光伏组件

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1464226B2 (de) * 1962-12-19 1972-09-21 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum herstellen von elektrisch unsymmetrisch leitenden halbleiteranordnungen
FR1453086A (fr) * 1964-11-06 1966-04-15 Telefunken Patent Dispositif semiconducteur et procédé de fabrication d'un tel dispositif

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4887143A (en) * 1988-03-28 1989-12-12 Mitsubishi Denki Kabushiki Kaisha Semiconductor device

Also Published As

Publication number Publication date
US3666548A (en) 1972-05-30
DE2046833A1 (de) 1971-07-22
FR2075939A1 (enExample) 1971-10-15
DE2046833C3 (de) 1978-08-31
FR2075939B1 (enExample) 1974-09-20
GB1274726A (en) 1972-05-17
DE2046833B2 (de) 1977-12-29

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