JPS4911008A - - Google Patents

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Publication number
JPS4911008A
JPS4911008A JP47052271A JP5227172A JPS4911008A JP S4911008 A JPS4911008 A JP S4911008A JP 47052271 A JP47052271 A JP 47052271A JP 5227172 A JP5227172 A JP 5227172A JP S4911008 A JPS4911008 A JP S4911008A
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP47052271A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP47052271A priority Critical patent/JPS4911008A/ja
Publication of JPS4911008A publication Critical patent/JPS4911008A/ja
Pending legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP47052271A 1972-05-26 1972-05-26 Pending JPS4911008A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP47052271A JPS4911008A (ja) 1972-05-26 1972-05-26

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP47052271A JPS4911008A (ja) 1972-05-26 1972-05-26

Publications (1)

Publication Number Publication Date
JPS4911008A true JPS4911008A (ja) 1974-01-31

Family

ID=12910098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP47052271A Pending JPS4911008A (ja) 1972-05-26 1972-05-26

Country Status (1)

Country Link
JP (1) JPS4911008A (ja)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5051632A (ja) * 1973-09-07 1975-05-08
JPS50137627A (ja) * 1974-04-22 1975-10-31
JPS51117523U (ja) * 1975-12-09 1976-09-24
JPS5642825A (en) * 1979-09-14 1981-04-21 Clarion Co Ltd Compensating circuit for data reading clock
JPS58121851A (ja) * 1982-01-14 1983-07-20 Canon Inc 同期回路
JPS6128251A (ja) * 1984-07-19 1986-02-07 Nitsuko Ltd クロツク同期方式
JPS61120538A (ja) * 1984-11-15 1986-06-07 Nec Corp 多方向多重通信装置
JPH01190043A (ja) * 1988-01-25 1989-07-31 Fujitsu Ltd クロック再生回路
JPH0353629A (ja) * 1989-07-21 1991-03-07 Hitachi Ltd ビット位相同期回路
US5012198A (en) * 1988-09-29 1991-04-30 Mitsubishi Rayon Company, Ltd. Digital PLL circuit having reduced lead-in time

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5051632A (ja) * 1973-09-07 1975-05-08
JPS5633751B2 (ja) * 1973-09-07 1981-08-05
JPS50137627A (ja) * 1974-04-22 1975-10-31
JPS51117523U (ja) * 1975-12-09 1976-09-24
JPS5642825A (en) * 1979-09-14 1981-04-21 Clarion Co Ltd Compensating circuit for data reading clock
JPS58121851A (ja) * 1982-01-14 1983-07-20 Canon Inc 同期回路
JPS6128251A (ja) * 1984-07-19 1986-02-07 Nitsuko Ltd クロツク同期方式
JPH0584691B2 (ja) * 1984-07-19 1993-12-02 Nitsuko Ltd
JPS61120538A (ja) * 1984-11-15 1986-06-07 Nec Corp 多方向多重通信装置
JPH01190043A (ja) * 1988-01-25 1989-07-31 Fujitsu Ltd クロック再生回路
US5012198A (en) * 1988-09-29 1991-04-30 Mitsubishi Rayon Company, Ltd. Digital PLL circuit having reduced lead-in time
JPH0353629A (ja) * 1989-07-21 1991-03-07 Hitachi Ltd ビット位相同期回路

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