JPH1187559A - Insulating base material supporting wiring layer, manufacture thereof, and semiconductor device provided therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is so lessened in size as to be as small as a semiconductor chip and improved in electrical properties and where a wiring layer is enhanced in degree of integration by a method wherein the wiring layer is formed of a sheet of metal and made solid in an insulating base material. SOLUTION: A wiring layer 5 formed of a sheet of metal is supported with an insulating base 4, whereby the surface 4a and backside 4b of the insulating base 4 are electrically connected together without additionally providing a through-hole to the insulating base 4. By this setup, a space where a through- hole is formed is not required, so that a ball grid array(BGA) semiconductor device 1 can be lessened in size. Moreover, a through-hole can be dispensed with, and the wiring layer 5 can be enhanced in degree of integration. Furthermore, the wiring layer 5 is formed of a sheet of metal and excellent in electrical properties. Therefore, the BGA semiconductor device 1 can be improved in electrical properties.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulating substrate carrying a wiring layer having a function as a part of an external connection conductor for connecting a semiconductor chip to an external circuit, a method for manufacturing the same, and the insulating substrate. Accordingly, the present invention relates to a semiconductor device capable of fine wiring, having excellent electric characteristics, and being reduced in size to approximately the same size as a semiconductor chip.

[0002]

2. Description of the Related Art As a conventional semiconductor device having a large number of input / output terminals, a quad flat package (hereinafter referred to as QFP) is known. The QFP type semiconductor device is formed by mounting a semiconductor chip on a lead frame by die bonding, performing wire bonding, and then resin sealing. In this QFP type semiconductor device, terminals are one-dimensionally arranged on a peripheral portion.

Another example of a conventional semiconductor device is a ball grid array (hereinafter referred to as BGA) type semiconductor device. An example of the BGA type semiconductor device 1 is shown in FIG. The BGA type semiconductor device 1 includes a wiring board 14, a semiconductor chip 3, a molding resin 2, and solder balls 8. The semiconductor chip 3 is mounted on the wiring substrate 14 by die bonding, and is connected via a wire 9 to a wiring layer (not shown) formed on the wiring substrate 14. The solder balls 8 are two-dimensionally arranged on the back surface of the wiring board 14.

FIG. 17 shows the BGA type semiconductor device 1 described above.
3 shows a structural example near the solder ball 8.
As shown in this figure, the main surface 14a of the wiring board 14
The conductor pattern 16a is formed thereon, and the conductor pattern 16b is formed on the back surface 14b of the wiring board 14. A through hole 15 is provided in a peripheral portion of the wiring board 14, and conductor patterns 16a and 16b are connected through a hollow conductor formed so as to surround the through hole 15. The conductor pattern 16a is connected to the semiconductor chip 3, and the conductor pattern 16b is connected to the solder ball 8.

[0005]

In the above-mentioned QFP type semiconductor device, since the external terminals are one-dimensionally arranged on the periphery,
There is a problem that the size of the semiconductor device becomes considerably larger than the chip size.

On the other hand, in the BGA type semiconductor device 1, through holes 15 have to be formed in order to make the main surface and the back surface of the wiring board 14 conductive. Since this through hole 15 is provided in the peripheral portion of the wiring board 14, the BG
Similarly, the A-type semiconductor device 1 has a problem that the size of the semiconductor device is larger than the chip size. There is also a problem that a new process for forming the through hole 15 is required.

The present invention has been made to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which can be reduced in size to a size substantially equal to that of a semiconductor chip, enables high integration of a wiring layer, and has excellent electric characteristics.

[0008]

The insulating base material according to the present invention carries a wiring layer functioning as a part of an external connection conductor for connecting a semiconductor chip to an external circuit. The insulating base has a main surface and a back surface. The wiring layer is formed by etching a single metal plate, extends from the main surface to the back surface, penetrates the insulating base material, and extends on the main surface or the back surface, and is solid in the insulating base material.

As described above, the wiring layer carried on the insulating base material according to the present invention is formed by etching a single metal plate, penetrating from the main surface to the back surface of the insulating base material, and Solid in wood. This wiring layer makes it possible to conduct between the main surface and the back surface of the insulating base material. More specifically, the wiring layer is formed by etching a single metal plate having a portion locally penetrating the insulating base material and carried by the insulating base material. Therefore, it is not necessary to form the through-hole 15 and conduct between the main surface and the back surface as in the conventional example. As a result, by using the insulating base material according to the present invention, it is possible to reduce the size of the semiconductor device to the same extent as a semiconductor chip. Further, since the formation of the through hole 15 can be omitted as described above, the integration of the wiring layer can be increased. Further, since the wiring layer is formed by etching a single metal plate, the wiring layer is formed of an integral metal and becomes solid in the insulating base material. Therefore, the electrical characteristics of the wiring layer are also improved. As described above, by using the insulating base material according to the present invention, it is possible to obtain a semiconductor device which can be reduced in size to about the same size as a semiconductor chip, can be highly integrated with a wiring layer, and has excellent electric characteristics.

A semiconductor chip is mounted on the main surface of the insulating base. Then, one end of the solid portion located in the insulating base in the wiring layer may be exposed to the main surface, and the wiring layer and the semiconductor chip may be connected at the one end. At this time, the wiring layer includes a portion extending from the other end of the solid portion to the back surface of the insulating base material.

By exposing one end of the solid portion of the wiring layer to the main surface as described above, for example, when connecting the semiconductor chip to the wiring layer using a bonding wire, one end of the solid portion is bonded to the bonding pad. It can be used as a unit. Accordingly, it is not necessary to form a bonding pad portion by extending the wiring layer on the main surface of the insulating base material, and it is possible to provide a large number of bonding pad portions on the main surface. Thus, the number of external terminals of the semiconductor device can be increased.

A method for manufacturing an insulating base material carrying a wiring layer according to the present invention includes the following steps. That is, the first and second mask layers are formed on the main surface and the back surface of the metal plate, respectively. A recess is formed in the main surface of the metal plate by etching the metal plate from the main surface using the first mask layer. An insulating base material is formed by filling the concave portion with an insulating resin. The surface of the insulating base material is selectively exposed by etching the metal plate from the back surface using the second mask layer.

[0013] As described above, the first mask layer is used to etch the main surface of the metal plate to form a recess in the metal plate, and the recess is filled with an insulating resin. Can be formed. In addition, since the concave portion is filled with the insulating resin, it is possible to provide a portion of the metal plate that locally penetrates the insulating base material. Then, the surface of the insulating base material is selectively exposed by etching the metal plate from the back surface using the second mask layer. This makes it possible to pattern the metal plate supported on the insulating base material. As a result, a wiring layer penetrating the insulating base material and supported by the insulating base material and formed of an integral metal is formed. With such a wiring layer, conduction between the main surface and the back surface of the insulating base material can be conducted, so that it is not necessary to form the through hole 15 unlike the conventional example. Thereby, the effect as described above is obtained.

According to the present invention, there is provided a semiconductor device having an insulating base material carrying a wiring layer, comprising: an insulating base material; a semiconductor chip;
And a mold resin. The insulating base has the above-described configuration, and the semiconductor chip is mounted on the main surface of the insulating base and connected to one end of the wiring layer. The mold resin is formed on the main surface so as to cover the semiconductor chip. Further, the wiring layer carried on the insulating base is solid in the insulating base.

As described above, the semiconductor device according to the present invention has the above-described insulating base material. By having such an insulating base material, it is possible to conduct between the main surface and the back surface of the insulating base material by the wiring layer without separately forming a through hole in the insulating base material. Thus, the size of the semiconductor device can be reduced to approximately the same size as the semiconductor chip. Further, since it is not necessary to form a through hole in the insulating base material, the wiring layer can be highly integrated, and the number of external terminals can be increased. Furthermore, since the wiring layer functioning as a part of the external connection conductor is made of an integral metal, the electrical characteristics of the external connection conductor can be improved. That is, according to the present invention, a miniaturized and high-performance semiconductor device can be obtained.

One end of the above wiring layer is constituted by one end of a solid portion of the wiring layer located in the insulating base material, and may be exposed on the main surface. At this time, the wiring layer may have another end disposed on the back surface of the insulating base material, and a connection portion connecting one end of the wiring layer to the other end. Then, a protective layer may be formed on the back surface so as to expose the other end and cover the connection portion, and an external terminal portion may be formed on the other end.

By using one end of the solid portion of the wiring layer as one end of the wiring layer as described above, the semiconductor chip and the wiring layer are connected without extending the wiring layer on the main surface of the insulating base material. It becomes possible. This can also contribute to higher integration of the wiring layer.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention and its modifications will be described below with reference to FIGS. FIG. 1 is a block diagram of B according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the GA type semiconductor device 1.

As shown in FIG. 1, the BGA type semiconductor device 1 includes a mold resin 2, a semiconductor chip 3, an insulating base material 4, a wiring layer 5, and solder balls 8.

The insulating substrate 4 is made of at least one material selected from an epoxy resin, an epoxy acrylate resin, a polyimide resin, and a polyphenylene sulfide resin.
Alternatively, it is preferable that these resins are made of a material obtained by adding an inorganic or organic filler. The insulating base 4 has a main surface 4a and a back surface 4b, and the semiconductor chip 3 is mounted on the main surface 4a. The solder balls 8 are two-dimensionally arranged on the back surface 4b of the insulating base material 4.

The insulating base material 4 is moved from the main surface 4a to the back surface 4a.
Wiring layer 5 is formed to penetrate through b. Wiring layer 5
Is formed by etching a single metal plate and is made of an integral metal. In this case,
A large number of wiring layers 5 are carried on the insulating base 4.
The wiring layer 5 is preferably made of, for example, a metal having good conductivity and capable of being etched, such as copper, iron, an iron-nickel alloy, and aluminum.

The wiring layer 5 includes a bonding pad portion 5a exposed on the main surface 4a of the insulating base material 4, a land portion 5c disposed on the back surface 4b of the insulating base material 4, a bonding pad portion 5a and the land portion 5c. And a connecting portion 5b including the above-described solid portion. The bonding pad portion 5a
The wiring layer 5 is constituted by one end of a solid portion located in the insulating base material 4. By using one end of the solid portion in the wiring layer 5 as the bonding pad portion 5a, it is not necessary to extend the wiring layer 5 on the main surface 4a of the insulating base material 4. Thereby, the main surface 4 of the insulating base material 4
a, more bonding pad portions 5a can be formed, and high integration of the wiring layer 5 becomes possible.

On the other hand, the connecting portion 5b is
Since it has a portion extending upward, the land portion 5c can be arranged at a desired position on the back surface 4b of the insulating base material 4. That is, it is possible to improve the degree of freedom in the arrangement of the land portions 5c. Solder balls 8 are formed on land portions 5c with bonding layers 7 interposed therebetween. The solder balls 8 function as external terminals.

By supporting the wiring layer 5 made of an integral metal as described above on the insulating base material 4, the main surface 4a and the back surface 4b of the insulating base material can be provided without separately providing through holes in the insulating base material 4. It is possible to conduct between them.
Thus, it is not necessary to secure a space for forming a through hole, and the size of the BGA type semiconductor device 1 can be reduced as compared with the conventional example. In addition, since the through holes can be omitted, the wiring layer 5 can be highly integrated. Further, since the wiring layer 5 is made of an integral metal, its electric characteristics are also good. Therefore, B
The electrical characteristics of the GA semiconductor device 1 can also be improved.

In the case shown in FIG. 1, the semiconductor chip 3 and the wiring layer 5 are connected by the wire 9, but the wiring layer 5 and the semiconductor chip 3 are connected by flip chip bonding using a conductive bump such as an Au bump. May be connected. In this case, B is more than the case shown in FIG.
The size of the GA semiconductor device 1 can be reduced, and the size of the BGA semiconductor device 1 can be reduced to approximately the same size as the semiconductor chip 3.

Referring again to FIG. 1, back surface 4b is formed so as to cover connection portion 5b extending on back surface 4b of insulating base material 4.
A solder mask 6 is formed thereon. The solder mask 6 is provided so as to cover the connection part 5b except for the land part 5c, and is made of, for example, a solder resist.
The solder mask 6 may be made of the same material as the insulating base material 4 as long as it can protect the connection portion 5b.

Next, the planar arrangement of the wiring layer 5 will be described with reference to FIGS. FIG. 4 is a plan view of the insulating base 4 viewed from the main surface 4a side, and FIG. 5 is a plan view of the insulating base 4 viewed from the back side 4b side.

First, referring to FIG. 4, bonding pad portions 5a are arranged in a line along the periphery of insulating base material 4. A solid portion of the wiring layer 5 exists directly below the bonding pad portion 5a. By providing the bonding pad portion 5a directly above the solid portion in this manner, it is not necessary to extend the wiring layer 5 on the main surface 4a, and high integration of the wiring layer 5 becomes possible as described above. Note that the bonding pad portions 5a may be arranged in a staggered manner.

Next, referring to FIG. 5, the connecting portion 5b has a portion extending from the other end of the solid portion to the back surface 4b. A land 5c is provided at the tip of the connection 5b. As shown in FIG. 5, the land portion 5c is arranged at a desired position on the back surface 4b by the connection portion 5b. As described above, the land 5c can be arranged at a desired position by the connecting portion 5b.
It is possible to improve the degree of freedom of the arrangement.

Next, a modification of the embodiment shown in FIG. 1 will be described with reference to FIGS.

Referring to FIG. 2, in this modification, a metal pillar 10 is provided instead of solder ball 8. Other structures are the same as those shown in FIG.
Examples of the material of the metal column 10 include copper and the like.

Next, another modified example will be described with reference to FIG. In this modification, a concave portion 4c is provided on the main surface 4a of the insulating base material 4, and the semiconductor chip 3 is arranged in the concave portion 4c. Other structures are the same as those shown in FIG. 2 and 3, flip-chip bonding can be employed as in the case shown in FIG.

Next, a method of manufacturing the BGA type semiconductor device 1 shown in FIG. 1 will be described with reference to FIGS. 6 to 15 are cross-sectional views showing first to tenth steps of the manufacturing process of the BGA type semiconductor device 1 shown in FIG.

First, referring to FIG. 6, a metal plate 11 made of a material such as copper is prepared, and pretreatments such as degreasing and leveling are performed on main surface 11a and back surface 11b of metal plate 11. next,
As shown in FIG. 7, photoresists 12a and 12b are applied on both main surface 11a and back surface 11b of metal plate 11. The photoresists 12a and 12b may be either a liquid photoresist or a dry film.
In the case of a liquid photoresist, it is necessary to dry the photoresist after coating.

Next, as shown in FIG. 8, the photoresists 12a and 12b are each patterned into a predetermined shape. More specifically, the photoresist 12a is patterned by exposing and developing using a photomask on which a pattern of the bonding pad 5a is formed, and is exposed using a photomask on which a pattern of the connecting portion 5b and the land 5c is formed. The photoresist 12b is patterned by post-development.

Thereafter, as shown in FIG. 9, an adhesive tape 13a is attached to the back surface 11b of the metal plate 11 so as to cover the photoresist 12b. Note that the photoresist 12b may be protected by a resin. The metal plate 11 is etched using the photoresist 12a as a mask while the back surface of the metal plate 11 is protected by the adhesive tape 13 and the like. Thereby, as shown in FIG. 10, a concave portion 11c is formed on the main surface 11a side of the metal plate 11. Then, the metal plate 11 is washed with water and then dried.

Next, as shown in FIG. 11, the recess 11c is filled with an insulating resin. Thereby, the insulating base material 4 in which the metal plate 11 is locally penetrated is formed. The filling method may be either filling with a dispenser or transfer molding, and is cured after filling. For cavity up and cavity down shapes,
After application by the dispenser, the resin is pressed down by the mold. In the case of transfer mold, a dedicated mold is prepared.

Next, as shown in FIG. 12, after filling and curing the resin, an adhesive tape 13b is attached to the insulating base material 4 so as to cover the photoresist 12a. Also in this case, a protective layer such as a resin may be formed instead of the adhesive tape 13b. The metal plate 11 is etched from the back surface 11b while the main surface 11a of the metal plate 11 is protected in this manner. Thereby, the back surface 4b of the insulating base material 4 is selectively exposed, and the connection portion 5b extending on the back surface 4b is provided.
And a land portion 5c.

The etching solution for the metal plate 11 is F when the metal plate 11 is iron or an iron-nickel alloy.
eCl ₃ can be used, and in the case of copper and copper alloy, FeCl ₃ is used.
₃ , CuCl ₂ or the like can be used.

Next, referring to FIG. 13, by removing the adhesive tape 13b and the photoresists 12a and 12b, the wiring layer 5 carried on the insulating base material 4 is formed. The wiring layer 5 includes a bonding pad portion 5a exposed on the main surface 4a of the insulating base material 4, a land portion 5c disposed on the back surface 4b of the insulating base material 4, a land portion 5c and the bonding pad portion 5a. And a connection portion 5b for connecting the. In addition, instead of the adhesive tape 13b functioning as an etching protection film, a photoresist 12 is used.
Resins which can be peeled off by the peeling liquids a and 12b may be used. In this case, only one peeling step is required.

Next, referring to FIG. 14, the surface of bonding pad portion 5a is plated with Ag or Au. Then, a solder resist is applied on the back surface 4b of the insulating base material 4 so as to cover the connection portions 5b except for the land portions 5c.
After the solder resist is cured, the land portion 5c and the solder ball 8 are joined by using a joining layer 7 made of solder or a conductive adhesive.

Next, as shown in FIG. 15, the semiconductor chip 3 is mounted on the main surface 4a of the insulating base material 4 with a die bond adhesive, and wire bonding is performed. After that, the mold resin 2 is formed so as to cover the semiconductor chip 3. The semiconductor device 1 shown in FIG.
Is formed. In the above-described embodiment, the wiring layer 5 extends only on the rear surface 4b of the insulating base material 4, but may extend on the main surface 4a.

As described above, one embodiment of the present invention and its modified example have been described. However, the embodiment disclosed this time is an example in all respects and is not restrictive. Should be considered. The scope of the present invention is defined by the terms of the claims, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a semiconductor device according to one embodiment of the present invention.

FIG. 2 is a sectional view showing a modification of the semiconductor device shown in FIG.

FIG. 3 is a sectional view showing another modification of the semiconductor device shown in FIG. 1;

FIG. 4 is a plan view of one example of the insulating base material according to the present invention as viewed from the main surface side.

FIG. 5 is a plan view of an example of the insulating base material according to the present invention as viewed from the back surface side.

FIG. 6 is a cross-sectional view showing a first step of the manufacturing process of the semiconductor device shown in FIG.

FIG. 7 is a sectional view showing a second step in the manufacturing process of the semiconductor device shown in FIG. 1;

FIG. 8 is a sectional view showing a third step of the manufacturing process of the semiconductor device shown in FIG. 1;

FIG. 9 is a cross-sectional view showing a fourth step in the process of manufacturing the semiconductor device shown in FIG.

10 is a fifth view of the manufacturing process of the semiconductor device shown in FIG. 1;
It is sectional drawing which shows a process.

FIG. 11 is a sixth view of the manufacturing process of the semiconductor device shown in FIG. 1;
It is sectional drawing which shows a process.

FIG. 12 is a seventh view of the manufacturing process of the semiconductor device shown in FIG. 1;
It is sectional drawing which shows a process.

FIG. 13 is an eighth view of the manufacturing process of the semiconductor device shown in FIG. 1;
It is sectional drawing which shows a process.

FIG. 14 is a ninth manufacturing process of the semiconductor device shown in FIG. 1;
It is sectional drawing which shows a process.

FIG. 15 shows a first step of the manufacturing process of the semiconductor device shown in FIG. 1;
It is sectional drawing which shows 0 process.

FIG. 16 is a partial cross-sectional view illustrating an example of a conventional semiconductor device.

FIG. 17 is a cross-sectional view showing a structural example near a solder ball in a conventional semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 BGA type semiconductor device 2 Mold resin 3 Semiconductor chip 4 Insulating base material 4a, 11a, 14a Main surface 4b, 11b, 14b Back surface 4c, 11c Concave portion 5 Wiring layer 5a Bonding pad portion 5b Connection portion 5c Land portion 6 Solder mask 7 Bonding layer 8 Solder ball 9 Wire 10 Metal column 11 Metal plate 12a, 12b Photoresist 13a, 13b Adhesive tape

Claims (5)

[Claims] 1. An insulating base material carrying a wiring layer functioning as a part of an external connection conductor connecting a semiconductor chip and an external circuit, wherein the insulating base material has a main surface and a back surface, The wiring layer is formed by etching a single metal plate, extends through the insulating base from the main surface to the back, extends on the main surface or on the back, and extends in the insulating base. A solid insulating base material carrying a wiring layer. 2. The semiconductor chip is mounted on the main surface, one end of a solid portion located in the insulating base in the wiring layer is exposed to the main surface, and the wiring layer is connected to the wiring layer at the one end. The insulating base material carrying the wiring layer according to claim 1, wherein the wiring layer is connected to a semiconductor chip, and the wiring layer includes a portion extending from the other end of the solid portion to the back surface. Forming a first mask layer on the main surface of the metal plate and forming a second mask layer on the rear surface of the metal plate; and etching the metal plate from the main surface using the first mask layer. Forming a recess on the main surface of the metal plate, forming an insulating base material by filling the recess with an insulating resin, and forming the metal from the back surface using the second mask layer. A step of selectively exposing the surface of the insulating base material by etching a plate; and a method of manufacturing an insulating base material carrying a wiring layer, comprising: 4. An external connection having a main surface and a back surface, which is formed by etching a single metal plate, extends from the main surface to the back surface, extends on the main surface or the back surface, and has an external connection. An insulating base material supporting a wiring layer functioning as a part of a conductor; a semiconductor chip mounted on a main surface of the insulating base material and connected to one end of the wiring layer; A molding resin formed on a main surface, wherein the wiring layer is solid in the insulating base, and has an insulating base supporting the wiring layer. 5. One end of the wiring layer is constituted by one end of a solid portion of the wiring layer located in the insulating base material, and is exposed on the main surface. A protection layer having a second end disposed on the back surface and a connection portion for connecting one end of the wiring layer to the other end, and exposing the other end to cover the connection portion; The semiconductor device according to claim 4, wherein an external terminal portion is formed on the other end.