JPH1173739A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL(phase locked loop) circuit without being affected by noise by adjusting the loop gain even for signals recorded in the format where no PLL(phase locked loop) pull-in section exists, increasing the loop gain and promoting pull-in when unlocked, and decreasing the loop gain when locked. SOLUTION: A mask timing generating section 102 generates MASK signals based on the phase error signal UP signal and DOWN signal or the rising/falling edge signal of the pulse signal and the control signal supplied externally to output to a mask gate 103. The mask gate 103 is controlled by the MASK signals generated by a mask timing generating section 102 to make a selection on whether to mask or pass the phase error signals outputted from a phase comparator 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PLL (Phase)
More particularly, the present invention relates to a reproduction PLL circuit for converting an information signal into a digital signal, recording the information signal on a recording medium such as a tape, a card, or a disk, and reproducing the recorded signal.

[0002]

2. Description of the Related Art Conventionally, a PLL circuit for reproducing a digitally recorded information signal has been used for generating a reference clock for reading digitally recorded data. In particular, for a clock in which the change point of a digitally recorded signal is not constant over time, a pulse signal is generated by extracting the edge of the digitally recorded signal, and the pulse component is used to generate a continuous pulse signal. It can be generated as a pulse signal.

First, problems of the PLL circuit will be described with reference to a block diagram of a first well-known PLL circuit shown in FIG.

The PLL circuit shown in FIG. 12 outputs a phase error signal proportional to the phase difference between a reference signal and a signal to be compared, and a phase comparator 1201 which inputs a phase error signal and outputs a current corresponding thereto. A charge pump 1202 and a loop filter 1203 which is an important circuit element for smoothing an output signal of the charge pump to output a control signal and determining a circuit configuration, an order, and a response characteristic of a PLL circuit.
A VCO (Voltage Controlled Oscillator) 1204, which is an oscillator whose output frequency changes according to a control signal from the loop filter 1203;
And a frequency divider 1205 for dividing the frequency of the output frequency.

In the above-described PLL circuit, in order to shorten the pull-in time of the PLL circuit, it is necessary to increase the loop gain and increase the response speed. On the other hand, after the signal is locked, P
It is necessary to prevent an excessive response of the LL circuit and to stabilize the PLL circuit. Therefore, once the PLL circuit is locked, it is necessary to lower the loop gain to lower the response speed.

In order to reduce the response speed of the PLL circuit, there are generally the following methods. (1) Decrease the gain constant of the phase comparator 1201. (2) The output current of the charge pump 1202 is reduced. (3) Increase the damping factor of the loop filter 1203. (4) The bandwidth of the loop filter 1203 is narrowed. (5) Decrease the FV (frequency-voltage) conversion gain constant of the VCO 1204.

A PLL circuit for self-clocking for extracting a clock from a signal recorded on a recording medium such as a magnetic tape or a CD is disclosed in Japanese Patent Application Laid-Open No. 4-162263.

[0008] FIG. 13 is a diagram showing a second example disclosed in the above publication.
1 is a block diagram of a PLL circuit according to a conventional example. FIG.
, The phase comparator 1301 and the loop filter 130
3 and the VCO 1304 may be considered to be the same circuits as the phase comparator 1201, the loop filter 1203, and the VCO 1204 of the PLL circuit shown in FIG.

In this conventional example, the charge pumps are composed of two first charge pumps 1302a having the same characteristics and a second charge pump 1302a.
It is characterized by being constituted by a charge pump 1302b.

A monostable multivibrator (hereinafter referred to as "monomulti") 1308 is a circuit for outputting a high level for a certain period of time from the rise of the read gate signal.
Used to open gates 09 and 1310.

Next, the operation of the PLL circuit shown in FIG. 13 will be described.

The reproduction signal is a signal reproduced from an information recording medium (not shown) such as an optical disk, and the read gate signal is a signal generated by a controller (not shown). The read gate signal is output to the switch 1311 and used as a switching signal for the reproduction signal of the signal S1 input to the phase comparator 1301 and the reference constant clock.

The read gate signal is a mono-multi 13
When the signal is also input to 08, the mono multi 1308 outputs to the AND circuits 1309 and 1310 a signal S2 that goes high for a fixed time T from the rise of the read gate signal. As a result, the gates of the AND circuits 1309 and 1310 are open for the predetermined time T, and the phase comparator 13
01 from the first charge pump 30 through the AND circuits 1309 and 1310.
2b.

Therefore, during the period T in which the output signal S2 from the mono-multi 1308 is at the high level, the second charge pump 1302b operates simultaneously with the first charge pump 1302a which is always operating, so that the first charge pump 1302a Since the sum of the output current of the second charge pump 1302b and the output current of the second charge pump 1302b is twice the output current of the first charge pump 1302a, the loop gain of the PLL circuit increases, and the response speed of the PLL circuit can be increased. In order to reduce the response speed from this state,
The signal S2 is set to low level so that only the first charge pump 1302a operates.

However, in the above PLL circuit, P
It is necessary to generate a read gate signal by a controller provided separately from the LL circuit. For this reason, VFO or AM (Address) in which the read gate section cannot be set
A clock cannot be extracted from a reproduced signal in a format in which no Mark pattern exists by using this PLL circuit.

Further, when it is desired to set a large number of loop gains, charge pumps must be prepared by the number of the loop gains, and the circuit scale increases.

Further, a technique of a PLL circuit in which the stability of the PLL loop is maintained over a wide band by controlling the conversion gain of the VCO in the PLL loop in accordance with a desired frequency and the lock-up time is shortened is disclosed in Japanese Patent Application Laid-Open No. HEI-5-1993. -37370
No., published in Japanese Unexamined Patent Publication No.

FIG. 14 shows a third embodiment disclosed in the above publication.
1 is a block diagram of a PLL circuit according to a conventional example. This conventional PLL circuit includes a first programmable frequency divider 140
Fout / N divided by 4 and reference oscillator 14
07, a phase comparator 1401 that detects a phase difference from the reference clock f output from the reference clock f and outputs a phase error signal, a low-pass filter 1402 that smoothes the phase error signal, and an oscillation frequency that is changed by an output signal of the low-pass filter 1402. VCO 1403, a second programmable divider 1408 for dividing the output frequency of the VCO 1403, and a first programmable divider 1404 for dividing the output signal of the second programmable divider 1408. .

Next, the operation of the above-described PLL circuit will be described.

Output signal Fout of second programmable frequency divider 1408 obtained by dividing the output signal of VCO 1403 by M
Is frequency-divided by N by the first programmable frequency divider 1404, and the phase is compared with the reference clock f by the phase comparator 1401. Reference clock f and signal Fout / N
The PLL loop operates so that the phase difference between the two becomes zero, so that the relationship of Fout = N · f is satisfied.

Further, the loop gain G of the PLL circuit
Is represented by G = Kd · Fo · Ko / (MN). Here, Kd is the conversion gain of the phase comparator 1401, Fo is the conversion gain of the low-pass filter 1402, Ko is the conversion gain of the VCO, and N and M are the frequency divisions of the first and second program frequency dividers 1404 and 1408, respectively. Ratio.

In this conventional example, M. In the case of control to keep N constant, a control signal can be sent to the first voltage controlled oscillation circuit 1409 to control the conversion gain, and the loop gain can be set to a desired value for the output frequency. Therefore, it is possible to stabilize the operation over a wide band.

However, the above-mentioned PLL circuit is effective when used for the purpose of obtaining an output signal Fout N times the reference signal f, but is used for the purpose of self-clocking for extracting a clock from the recorded digital data itself. Is not suitable. In particular, when the change point of the recorded data is not constant, the clock cannot be extracted.

That is, the timing signal for reading data is the signal to be compared (reference signal f) input to the phase comparator 1401, and a frequency divider cannot be provided at the subsequent stage. That is, the frequency division ratio cannot be determined using a circuit configuration that does not affect the output frequency.

Further, if the reference signal is constant, even if the frequency division ratio of the programmable frequency divider is increased, the VCO 14
If the oscillation frequency of 03 increases, the loop gain G = Kd ·
Since Ko / (MN) in Fo · Ko / (MN) does not change, the loop gain of the entire PLL circuit does not change.

Also, the provision of a programmable frequency divider is not preferable because it increases the circuit scale, and when trying to set the frequency division ratio finely, the frequency division ratio becomes large and the oscillation frequency of the VCO 1403 becomes high accordingly. This makes it difficult to design the VCO and the VCO 1
Various problems occur, such as an increase in current consumption of the 403 and an oscillation output entering the circuit as noise.

Japanese Patent Application Laid-Open No. 7-302072 discloses an example of a PLL circuit in which the resistance of the phase circuit to noise is improved and the pull-in time is shortened. This PL
The L circuit includes a lockout detection unit, and further uses a gate unit that passes only a section including an edge timing for detecting an input synchronization signal.

However, in the above PLL circuit, the capture range is determined by the edge timing section. That is, if the window width in the edge timing section is in the N% range before and after the edge, the capture range is only N% at the maximum, and there is a problem that the width of the capture range cannot be expanded.

[0029]

Problems to be Solved by the Invention
In the PLL circuit described in Japanese Patent Publication No. 3 (KOKAI), since a read gate signal needs to be generated by a controller provided separately from the PLL circuit, a clock is extracted from a reproduced signal in a format in which a read gate section cannot be set. Can not.

Further, when it is desired to set a large number of gains, it is necessary to prepare charge pumps corresponding to the number, and there is a disadvantage that the circuit scale is increased.

The PLL circuit described in Japanese Patent Application Laid-Open No. Hei 5-37370 is difficult to use for the purpose of self-clocking for extracting a clock from recorded digital data itself. In particular, when the change point of the recorded data is not constant, the clock cannot be extracted.

Further, if the reference signal is constant, even if the frequency division ratio of the programmable frequency divider is increased, the VCO 14
If the oscillation frequency of 03 increases, the loop gain G = Kd ·
Since Ko / (MN) in Fo · Ko / (MN) does not change, there is a problem that the loop gain of the entire PLL circuit cannot be changed.

Also, providing a programmable frequency divider is not preferable because it increases the circuit scale, and when trying to set the frequency division ratio finely, the frequency division ratio increases and the oscillation frequency of the VCO 1403 increases accordingly. This makes it difficult to design the VCO and the VCO 1
Various problems occur, such as an increase in current consumption of the 403 and an oscillation output entering the circuit as noise.

In the PLL circuit described in Japanese Patent Application Laid-Open No. 7-302072, in a configuration in which an edge timing section is provided and a reproduced signal passes only in that section, a signal having a jitter larger than the width of the edge section is used. Cannot follow, so that the recording signal cannot be read. Therefore, the capture range and the conversion gain of the phase comparator
There are significant restrictions on the system configuration.

Therefore, an object of the present invention is to adjust the loop gain even for a signal recorded in a format in which there is no PLL lock-in section, to increase the loop gain when unlocking is not performed, to speed up the locking, and to lock the loop. The object of the present invention is to provide a PLL circuit which has a low loop gain and is strong against noise.

Another object of the present invention is to provide a PLL circuit which does not require a read gate section to be set by a controller or the like.

Another object of the present invention is to provide a PLL circuit which can set several types of loop gains using a small number of circuit elements.

It is another object of the present invention to provide a PLL circuit having a wide capture range without increasing the maximum frequency of a VCO when extracting a clock from a digitally recorded signal.

[0039]

Therefore, a PLL circuit according to the present invention detects a phase difference between a reference signal having a constant frequency or a reproduced signal whose signal change point is not constant in time and a signal to be compared, and detects a phase difference. In a PLL circuit having a phase comparator that outputs an error signal, a part of the phase error signal or the output signal that is different from the reference signal or the reproduced signal and the phase error signal of the phase comparator and the signal to be compared. It is characterized in that it is provided with a mask means for controlling whether to pass or block all.

[0040]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a PLL circuit according to the present invention. In FIG. 1, a phase comparator 101 generally has two input terminals, and an UP signal which is a phase error signal corresponding to a difference between a reference signal (reproduced signal) input to these input terminals and a signal to be compared. And DOW
Outputs N signal. Since the PLL loop operates so that the phase error signal becomes 0, the change points of the reference signal and the compared signal coincide with each other when the PLL circuit is locked.

The mask timing generator 102 generates a MASK signal based on a phase error signal obtained by the phase comparator 101 or a rising / falling edge signal of a pulse signal and an externally applied control signal, and generates a mask gate. Output to 103.

The mask gate 103 is controlled by the MASK signal generated by the mask timing generator 102, and selects whether to mask or pass the phase error signal output from the phase comparator 101.

The charge pump 104 is connected to the mask gate 1
The phase error signal, that is, the UP signal and the DOWN signal, which are the outputs of the phase comparator 101 that has been permitted to pass by S03, is output as a desired current, that is, a POMP signal.

The loop filter 105 smoothes the current output of the charge pump 104 and outputs it as a voltage or a current. The loop filter 105 is generally a low-pass filter, and a type configured using a resistor and a capacitor, a type configured using an operational amplifier, and the like are used.

The VCO 106 is an oscillator whose oscillation frequency changes according to the output voltage or output current of the loop filter 105. The frequency divider 107 divides the output frequency of the VCO 106 to a desired frequency.

Next, the operation of the PLL circuit according to the present embodiment will be described with reference to the block diagram of FIG. 1 and the timing chart shown in FIG.

The reference signal (reproduced signal) input to the phase comparator 101 in FIG. 1 includes a reference signal A in which signal change points occur at regular intervals as shown in FIG. The time interval from the fall to the rise of the pulse signal is referred to the sampling interval T, and the minimum time interval from the rise to the fall of the pulse signal or the minimum time interval from the fall to the rise of the pulse signal is the minimum inversion interval Tm.
in, the maximum time interval from the rise to the fall of the pulse signal or the maximum time interval from the fall to the rise of the pulse signal is the maximum inversion interval Tmax, and the minimum inversion interval T
A reference signal B such that a change point generated by imposing a constant condition between min and a maximum inversion interval Tmax is not temporally constant.
It can be roughly divided into two.

A signal such as the reference signal B whose change point with time is not constant is a signal obtained by converting a digital signal based on a certain rule, and this conversion is generally called modulation. This modulation includes NRZ (Non Return Zero Zero).
o), PE (Phase Encoding), MFM
(Modified Frequency Modul
), EFM (Eight to Fourt)
The PLL circuit according to the present embodiment can be applied to any modulation method capable of self-clocking, except for a modulation method such as NRZ that cannot extract a clock.

The sampling interval T in FIG. 2 represents the time width of a channel bit, which is the minimum data unit of digital data, and a channel bit clock for reading the channel bit is generated by the PLL circuit according to the present embodiment. . A channel bit clock having a sampling interval T (hereinafter, referred to as a bit clock) is represented as a compared signal in FIGS.

Here, as shown in the reference signal C of FIG.
When a phase shift occurs between the reference signal and the compared signal (the delay / lead of the phase is defined as the delay / lead of the phase of the compared signal with respect to the reference signal), the phase comparator of FIG. Reference numeral 101 detects a phase difference between the reference signal C and the signal to be compared, and outputs an UP signal and a DOWN signal shown in FIG.

The mask timing generator 10 shown in FIG.
2, the duty ratio of the MASK signal is 50% as shown in FIG. 2, and the mask gate 103 shown in FIG. 1 masks the UP signal or the DOWN signal while the mask signal is at the high level, and the UP signal during the low level. Or DOW
If the N signal is passed, the output of the charge pump 104 becomes the POMP signal shown in FIG.

That is, in the period t1, the fall of the signal to be compared advances with respect to the rise or fall of the reference signal C, so that the phase comparator 101 masks the DOWN signal for delaying the phase of the signal to be compared with the mask gate. 103
Through the charge pump 104.

On the other hand, since the phase of the signal to be compared is delayed with respect to the reference signal C in the period t2, the phase comparator 101 supplies the UP signal for advancing the phase of the signal to be compared via the mask gate 103 to the charge pump. Output to 104.

However, the UP signals U1a and U2 shown in FIG.
a, U3a and the DOWN signals D1a, D2a, D3a
Since it coincides with the high level period of the MASK signal, it is masked by the mask gate 103 and the charge pump 104
Is not output to

On the other hand, the UP signals U1b, U2b, U3b and the DOWN signals D1b, D2b coincide with the low level period of the MASK signal, so that they pass through the mask gate 103 and are output to the charge pump 104.

Therefore, as shown in FIG. 2, the POMP signal which is the output signal of the charge pump 104 is １ ／ compared with the number of pulse signals when not masked by the mask gate 103, and the PLL circuit according to the present embodiment Is １ ／ compared to the case where the mask gate 103 passes all the phase error signals.

[0058]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described in detail, particularly in the case where the reference signal in FIG. 1 is an EFM modulation system used in a compact disk (CD) or the like.

The EFM modulation system is a modulation system capable of self-clocking, but the rising or falling point of a recording signal recorded on a CD or the like is not constant over time. In the EFM modulation method, digital data called recording symbols each composed of 8 bits is converted into a pattern composed of 14 channel bits. In the EFM modulation method, the minimum inversion interval Tmin is set to 3T and the maximum inversion interval Tma based on the sampling interval T in consideration of easy extraction of bit synchronization information, high-density recording, DC components of signals, and the like.
x is defined as 11T.

FIG. 3 is a timing chart in the EFM modulation system and a diagram showing positions of holes called pits recorded on the CD surface corresponding to the EFM signal. EFM
In the modulation method, digital data recorded as pits is read out using laser light (not shown) from a pickup, and converted into binary signals of "0" and "1". E
The FM signal has a data interval of 3T to 11T by definition, and the rising and falling edges of the signal are used to extract the clock from the data read from the pit.

This edge exists between 3T and 11T in the case of a normally recorded signal, and a continuous pulse train is generated using the frequency spectrum component of the continuous pulse repetition signal.

Next, the circuits of the phase comparator 101 and the mask timing generator 102 shown in FIG. 1 will be described with reference to the phase comparator 101 and the mask timing generator 102A shown in the gate level circuit diagram shown in FIG. This will be described in detail.

Referring to FIG.
Reference numeral 411 denotes a seven-stage shift register, and an EFM signal is input to the data input terminal D of the first-stage flip-flop 405. Also, the compared signal is input to the clock input terminal C and the inverted clock input terminal CB, respectively.
In order to perform edge delay for generating a MASK signal,
The compared signals are flip-flops 405, 407, 40
9 and 410 and inverted clock input terminals CB of flip-flops 406, 408 and 411, respectively.

The exclusive OR gate 401 is
The FM reproduction signal and the Q output of the flip-flop 405 are input, and an UP signal is output. Exclusive O
The R gate 402 receives the Q outputs of the flip-flops 407 and 408 and outputs a DOWN signal.

The exclusive OR gate 403 receives the Q outputs of the flip-flops 406 and 409,
Outputs a MASK signal. Similarly, Exclusive O
The R gate 404 receives the Q outputs of the flip-flops 409 and 411 and outputs a DOWNMASK signal. Here, the UPMASK signal and the DOWNMASK signal are
This is a MASK signal for the UP signal and the DOWN signal, and independently controls the passage of the UP signal and the DOWN signal and the control of the mask.

Next, the operation of the phase comparator 101 and the mask timing generator 102 shown in FIG. 4 will be described with reference to FIGS.
This will be described in detail with reference to the timing chart shown in FIG.

The EFM reproduced signal changes between 3T and 11T based on the sampling interval T and is input to the data input terminal D of the flip-flop 405. Flip-flop 405
To 411 operate at the rising edge of the clock input C, and the Q outputs of the flip-flops 405 to 411 have waveforms as shown in FIG.

Here, the exclusive OR gate 40
1 is an exclusive OR gate 4 because the EFM reproduction signal and the Q output of the flip-flop 405 are input.
The UP signal which is the output of 01 has a waveform as shown in FIG. That is, the UP signal in the locked state is
It is output from the exclusive OR gate 401 with a pulse width of T / 2 from the changing point of the EFM reproduction signal.

At time t1, the fall of the EFM reproduced signal is advanced with respect to the fall of the compared signal. In this case, the UP signal has a longer pulse width by the time width in which the phase of the EFM reproduced signal is advanced. Is output. That is,
Assuming that the EFM reproduction signal is advanced by αT with respect to the compared signal, the pulse width of the UP signal in this case is an increase in the pulse width due to the advance of the phase of the EFM reproduction signal to the width of the UP signal at the time of locking. Minutes, and becomes (1/2
+ Α) · T.

Conversely, at time t2, the rising of the EFM reproduction signal is delayed with respect to the falling of the compared signal. In this case, the UP signal has a shorter pulse width by the time width in which the phase of the EFM reproduction signal is delayed. That is, assuming that the EFM reproduction signal is delayed by βT with respect to the compared signal, the pulse width of the UP signal in this case is the pulse width due to the delay of the phase of the EFM reproduction signal from the width of the UP signal at the time of locking. Is subtracted, and is represented by (1 / 2−α) · T.

As can be seen from FIG. 5, the DOWN signal is output with a pulse width of T / 2 with a delay of 1T from the fall of the UP signal. However, the EFM reproduced signal and the compared signal (bit clock) are output. ) Has a phase difference,
It does not affect the pulse width of the OWN signal. That is, DO
The pulse width of the WN signal is fixed at T / 2 also at the time of locking and at times t1 and t2.

Therefore, at the time of locking, the UP signal and the D signal
Since the OWN signal has a pulse width of T / 2 and is input to the charge pump 104 by the same number of pulses, the POMP signal, which is the output signal of the charge pump 104, is smoothed by the loop filter 105 of FIG. Since there is no change, the compared signal (bit clock) which is the frequency-divided signal of the VCO 106 is also constant.

At time t1 when the phase of the EFM reproduction signal is advanced by αT with respect to the signal to be compared (bit clock).
, The pulse width of the UP signal is (1/2 + α).
The pulse width of the T and DOWN signals is T / 2, and the pulse width of the UP signal is increased by αT. Therefore, when the POMP signal, which is the output signal of the charge pump 104, is smoothed by the loop filter 105 of FIG. 1, the output voltage of the loop filter 105 caused by αT increases, and the VCO 10
6, the oscillation frequency of the VCO 106 and the frequency of the compared signal (bit clock), which is a frequency-divided signal, also increase.

That is, when the phase of the EFM reproduction signal is ahead of the phase of the compared signal (bit clock), the PLL circuit increases the frequency of the compared signal (bit clock) so that the phase difference becomes zero. Works.

On the other hand, at time t2 when the phase of the EFM reproduced signal lags behind the signal to be compared (bit clock) by βT, the pulse width of the UP signal becomes (1 / 2−β).
The pulse widths of the T and DOWN signals are T / 2, and the pulse width of the DOWN signal is increased by βT. For this reason, when the POMP signal, which is the output signal of the charge pump 104, is smoothed by the loop filter 105 of FIG. 1, the output voltage of the loop filter 105 caused by βT decreases, and VC
Since the control voltage of O106 also decreases, the oscillation frequency of VCO 106 and the frequency of the compared signal (bit clock), which is a frequency-divided signal, also decrease.

That is, when the phase of the EFM reproduction signal is behind the phase of the signal to be compared (bit clock), the PLL circuit reduces the frequency of the signal to be compared (bit clock) so that the phase difference becomes zero. Works.

Incidentally, in the EFM modulation method, the minimum inversion interval is set to 3T as described above. Therefore, when a signal is reproduced from a change point of less than 3T, the reproduced signal is likely to be an electrical noise or a signal defect.

As a result, at the change point less than 3T, the PLL
If the circuit configuration is devised so that the circuit does not react, a stable compared signal (bit clock) can be obtained. Therefore, the UP signal generated at the change point less than 3T and the DO signal
If the WN signal is masked and is not output to the charge pump 104 of FIG. 1, the oscillation frequency of the VCO 106 does not change, and malfunction due to noise or signal defects can be prevented.

In this embodiment, the UP signal and the DOW
N signals are output independently from the phase comparator 101 with a certain time width, so that the UP signal and the DOWN signal
It is also necessary to independently generate MASK signals for the signals.

After the UP signal and the DOWN signal are output from the phase comparator 101, as shown in FIG.
Tmask represented by the following equation (1) is obtained by securing a margin due to the characteristic variation of the OS transistor and similarly considering that the UP signal varies in the width of B shown in FIG.
It is preferable that the UP signal and the DOWN signal are masked.

Tmask = 3T−0.5T−0.5T−0.5 = 1.5T (1) where the first term is the minimum inversion interval Tmin, and the second term is UP
The width of the signal or the DOWN signal, the third term represents the margin of the portion A in FIG. 5, and the fourth term represents the margin of the portion B in FIG.

As described above, in response to the UP signal, the mask timing generator 10
2 is a UPMASK signal, and D
The control signal output from the mask timing generator 102 to the mask gate 103 in FIG.
This is the NMASK signal. The mask gate 103 in FIG.
The UPMASK signal and the DOWNMASK signal are masked at a high level to mask the UP signal or the DOWN signal, and are passed at a low level.

Further, t3 shown in FIG. 5 indicates a state where a change point of less than 3T is included in the EFM reproduction signal due to noise or the like. Also in this case, the UP signal generated at time t3 is masked by the UPMASK signal indicated by C and is not output to the charge pump of FIG.
Similarly, the DOWN signal is a DOWNMAS indicated by D in FIG.
Masked by the K signal.

Therefore, even if noise less than 3T occurs, P
The PLL circuit can be kept stable without changing the loop gain of the LL circuit.

Similarly, when the pulse width of the MASK signal is increased to mask a portion less than 4T, the PLL circuit naturally does not react to a change point of the EFM reproduction signal up to 3T.

Generally, the rate of change in the time width 3T is 35% to 40% when the rate of all change points up to the time width 11T is 100%. If this is appropriate, the number of phase comparisons is reduced by 35% to 40%, so that the loop gain G of the entire PLL circuit is reduced by 35% to 40%.
% Can be reduced.

Further, a LOCK signal indicating whether or not the PLL circuit is locked is supplied to the mask timing generation unit 10 shown in FIG.
When the PLL circuit is used to generate a MASK signal only when the PLL circuit is locked, the response speed can be increased while the loop gain is high when the PLL circuit is pulled in, and the pull-in can be performed quickly. .
On the other hand, after the pull-in is completed, the MASK signal prevents malfunctions due to electrical noise and signal defects, and realizes stable circuit operation.

As described above, if the LOCK signal is used as the control signal of the mask timing generation unit 102 in FIG. 1, a PLL circuit having a different PLL loop gain between the locked state and the unlocked state can be realized.

Similarly, the mask timing generator 102 can be controlled using a control signal from a microcomputer. That is, the MASK signal (UPMASK signal, D
OWN MASK signal) with a pulse width of 3T to 11T
Between 3T and 11
If it is possible to select between T, the microcomputer can set the loop gain of the PLL circuit at an arbitrary timing.

The above description is based on the assumption that the reference signal is EFM.
The loop gain of the PLL circuit can be arbitrarily set by controlling the pulse width of the mask signal, not only for the reproduction signal, but also for other modulation schemes or signals in which the time change point of the reproduction signal is constant.

Further, the control signal of the mask timing generation unit 102 is used as the control signal from the microcomputer and L
It is also possible to use both of the OCK signals together.

Note that the present invention is not limited to the configuration of the phase comparator and the output format of the UP signal and the DOWN signal described in the above embodiments.
If the circuit configuration is such that the mask gate is controlled by the MASK signal output from the mask timing generation unit and the phase error signal of the phase comparator is input to the charge pump via the mask gate, the technical idea of the present invention is realized. By applying this, it is possible to easily configure a PLL circuit that does not malfunction due to noise, signal defects, or the like while changing the loop gain of the PLL circuit or keeping the loop gain constant.

Further, the MASK signal may be output with an arbitrary pulse width when the phase comparison is performed, or may be generated at a constant cycle, in addition to the one shown in this embodiment.

If the reference signal is a reproduced signal whose change point does not match and has a frequency that is twice or more the frequency of the signal to be compared, the frequency of each of the reproduced signal and the signal to be compared is reduced to avoid erroneous locking. It is preferable to use a frequency comparison circuit that compares the two.

Next, a second embodiment of the present invention will be described with reference to FIG.

In FIG. 6, reference numeral 101 denotes a circuit diagram of the phase comparator 101 shown in FIG. 1 similar to that shown in FIG. 4 at the gate level, and reference numeral 102B denotes a mask timing generator 10 shown in FIG.
FIG. 2 is a circuit diagram showing a circuit diagram No. 2 at a gate level. The flip-flops 405 to 408 form a shift register, and a reproduction signal is input to the data input terminal D of the first-stage flip-flop 405.

Therefore, the exclusive OR gate 401 generates an UP signal, and the exclusive OR gate 402 outputs the DO signal, similarly to the phase comparator 101A shown in FIG.
Generate the WN signal.

The flip-flop 601 constituting the mask timing generation unit 102B is a toggle flip-flop which receives the UP signal as an inverted clock input.
Generate an UPMASK signal, which is a MASK signal for the signal. Similarly, the flip-flop 602 is connected to the DOWN
The signal is used as an inverted clock input to generate a DOWNMASK signal.

Next, the operations of the phase comparator 101 and the mask timing generator 102B shown in FIG. 6 will be described in detail with reference to the timing charts shown in FIGS.

The flip-flops 405 to 408 are shown in FIG.
The description is omitted because it is the same as the circuit configuration shown in FIG. Further, since the flip-flop 601 inputs the UP signal to the inverted clock input terminal CB, as shown in FIG.
Each time the P signal falls, the signal repeats a high level and a low level.

Similarly, the flip-flop 602 also outputs DOW
Each time the falling of the N signal occurs, it becomes a signal that repeats a high level and a low level. That is, the outputs of the flip-flop 601 and the flip-flop 602 are respectively U
Since the period is twice the period of the P signal and the DOWN signal,
If these are used as MASK signals, the UP signal and DO signal
The generation ratio of the WN signal can be halved.

This is because the loop gain of the PLL circuit is 1 /
2 as in the first embodiment.
By using the CK signal as a control signal and generating the MASK signal after the PLL circuit is locked (LO
When the CK signal is locked at a high level, the Reset signal shown in FIG. 6 is used). When the PLL circuit is pulled in, the loop gain is increased to increase the response speed, and after the lock, the loop gain is reduced to 1/2 and noise is reduced. A PLL circuit which operates stably and is strong can be realized. That is, although the loop gain is limited to １ ／, the circuit can be configured with a very small number of elements.

Further, the toggle flip-flop constituting the mask timing generation unit 102B is changed to a circuit configuration of a frequency divider or a counter, and the occurrence rate of the rising or falling of the MASK signal per unit time is reduced from 1/2 to 1 /
If it is changed to n (n is a natural number), the loop gain of the PLL circuit can be set arbitrarily.

Next, a PLL according to a third embodiment of the present invention will be described.
The circuit will be described with reference to the block diagram shown in FIG.

The PLL circuit shown in FIG. 8 uses a 1 / M frequency divider 801 to phase-shift a reference signal (reproduced signal) via a 1 / M frequency divider 801 without using the mask timing generator 102 and the mask gate 103 constituting the PLL circuit shown in FIG. This is a circuit method for inputting to the comparator 101. A 1 / M frequency divider 801 is a general programmable frequency divider or counter, and divides a reference signal (reproduction signal), which is an input signal, by M and outputs it. The frequency division ratio can be changed or the frequency division function can be turned ON / OFF by the control signal.

Next, a PLL according to a third embodiment of the present invention will be described.
The operation of the circuit will be described with reference to a timing chart shown in FIG. In FIG. 9, UP signal 1 and DO signal
The WN signal 1 includes an UP signal and a DOW output from the phase comparator 101 when a reference signal (reproduction signal) is input to the phase comparator 101 without passing through the 1 / M frequency divider 801 shown in FIG.
N signal.

When the 1 / M frequency divider 801 operates as a 2 frequency divider, the reference signal (reproduced signal) passed through the 1 / M frequency divider 801 becomes a 2 frequency divided reproduced signal shown in FIG. . The phase comparator 101 compares the phases of the frequency-divided reproduced signal and the compared signal (bit clock), and outputs the UP signal 2 and the DOWN signal 2 to the charge pump 104.

That is, the UP signal 2 and the DOWN signal 2
Is の of the appearance frequency of the UP signal 1 and the DOWN signal 1
Therefore, the loop gain of the PLL circuit is also halved. Therefore, if the 1 / M frequency divider 801 is used, the loop gain of the PLL circuit can be reduced to 1 / M without using MASK used in the PLL circuit according to the first embodiment.

Next, a PLL circuit according to a fourth embodiment of the present invention will be described with reference to the block diagram shown in FIG.

The PLL circuit shown in FIG. 10 corresponds to the P circuit shown in FIG.
In addition to the phase comparator 101, the charge pump 104, the loop filter 105, and the VCO 106 constituting the LL circuit, a 1 / M frequency divider 801 and 1004, a mask circuit 1001, and a detection edge delay circuit 1002 are added. Have been. Note that the 1 / N frequency divider 1003 in FIG.
Is a frequency divider having the same function as the frequency divider 107 shown in FIG.

The detection edge delay circuit 1002 detects a rising edge or a falling edge of the input reproduction signal, and delays the pulse signal by an arbitrary time to generate a signal M.
Generate an ASK signal. By controlling the delay time and pulse width of the pulse signal with the setting signal, the loop gain of the PLL circuit can be set to a desired value.

The mask circuit 1001 is a circuit for masking the phase error signal output from the phase comparator 101 with the MASK signal generated by the detection edge delay circuit 1002. As described above, if the mask circuit is turned ON / OFF by the lock signal, a PLL circuit having a different loop gain between the locked state and the unlocked state can be configured.

When the reproduction signal (reference signal) is divided by M using the 1 / M frequency divider 801, the reproduction signal (reference signal) having a non-constant temporal change point or a temporally constant change is obtained. Even for a reproduction signal (reference signal), the loop gain can be set finely.

FIG. 11 shows all the PLLs of the present invention described above.
FIG. 4 is a Bode diagram showing a relationship between an angular frequency and a loop gain when a loop gain of a circuit is changed. Assuming that the loop gain is 1 when the loop gain is 1 and 0 dB, when the loop gain is reduced to 1/2, 1/3 and 1/4, respectively, the loop gains expressed in dB are -6 dB, -9 dB and -12, respectively.
to dB.

In the above description, that is, in the description from the first embodiment to the fourth embodiment, the mask gate 103 or the mask circuit 1001 and the charge pump 10
4 are shown separately, but by connecting a MOS transistor or an analog switch to the source side or the drain side of the charge pump 104, the mask pump 103 or the mask circuit 1001 and the charge pump 104 can be configured as one circuit block. is there.

Further, the output form of the UP signal and the DOWN signal is not limited to that shown in the present embodiment, and the PLL circuit according to the present invention can be easily used as long as it is a binarized pulse signal.

[0117]

As described above, the PLL circuit of the present invention masks the phase error signal output from the phase comparator with the reference signal (reproduced signal) and the signal to be compared input to the phase comparator. And generate a mask signal of
Since the loop gain is not changed by dividing the signal to be compared by the frequency divider, the loop gain can be changed regardless of the input signal format or method.

Therefore, the present invention can be applied to an input signal without a read gate section or a PLL pull-in section.

Further, since the loop gain is determined by the pulse width and pulse interval of the mask signal for masking the phase error signal output from the phase comparator, the loop gain is set at an arbitrary value and at an arbitrary timing. Can be. Furthermore, since the circuit that determines the loop gain is simple,
There is an effect that the number of circuit elements is small.

Since the loop gain is not changed by dividing the signal to be compared by the divider, the VCO
May be the same as the frequency of the reproduction signal or the reference signal which is the input signal of the phase comparator. Therefore, VCO
It is not necessary to increase the oscillation frequency of

Further, in a period other than the mask period for masking the phase error signal output from the phase comparator, the phase error signal is the same as the operation of the conventional PLL circuit. Since the phase comparison range is not affected, the capture range can be widened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining an operation of the PLL circuit shown in FIG. 1;

FIG. 3 is a diagram showing a timing chart and pits for explaining an EFM modulation method.

FIG. 4 is a circuit diagram showing a phase comparator and a mask timing generator according to the first embodiment of the present invention.

FIG. 5 is a timing chart for explaining operations of a phase comparator and a mask timing generator shown in FIG. 4;

FIG. 6 is a circuit diagram illustrating a phase comparator and a mask timing generator according to a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining operations of a phase comparator and a mask timing generator shown in FIG. 6;

FIG. 8 is a block diagram showing a third embodiment of the present invention.

FIG. 9 is a timing chart for explaining an operation of the PLL circuit shown in FIG. 8;

FIG. 10 is a block diagram showing a fourth embodiment of the present invention.

FIG. 11 is a diagram showing the relationship between the angular frequency and the loop gain of the PLL circuit according to the present invention.

FIG. 12 is a block diagram of a PLL circuit according to a first conventional example.

FIG. 13 is a block diagram of a PLL circuit according to a second conventional example.

FIG. 14 is a block diagram of a PLL circuit according to a third conventional example.

[Explanation of symbols]

101, 1201, 1301, 1401 Phase comparator 102, 102A, 102B Mask timing generator 103 Mask gate 104, 1202 Charge pump 105, 1203, 1303 Loop filter 106, 1204, 1304, 1403 VCO 107, 1205 Divider 401 to 401 404 Exclusive OR gates 405 to 411, 601, 602 Flip-flops 801, 1004 1 / M frequency divider 1001 Mask circuit 1002 Detection edge delay circuit 1003 1 / N frequency divider 1302a First charge pump 1302b Second charge pump 1306 Latch 1308 Monostable multivibrator 1309, 1310 AND circuit 1311 switch 1402 low-pass filter 1404 first programmable frequency divider 1 07 reference oscillator 1408 second programmable frequency divider 1409 first voltage controlled oscillator

Claims (9)

[Claims] 1. A PLL circuit having a phase comparator for detecting a phase difference between a reference signal having a constant frequency or a reproduction signal whose signal change point is not temporally constant and a signal to be compared and outputting a phase error signal. Controlling whether or not to pass or block a part or all of the phase error signal is performed by the reference signal or the reproduction signal and an output different from the phase error signal of the phase comparator and the compared signal. A PLL circuit comprising mask means. 2. A PLL circuit having a phase comparator for detecting a phase difference between a reference signal having a constant frequency or a reproduction signal whose signal change point is not temporally constant and a compared signal and outputting a phase error signal. Using a signal obtained by delaying the reference signal or the reproduction signal by an arbitrary time, using a mask means for controlling whether to pass or block a part or all of the phase error signal. PLL circuit. 3. The reference signal or the reproduction signal is input to a first shift register having cascaded flip-flops, and the output of the shift register is input to a second shift register having cascaded flip-flops. An output signal of a first exclusive OR gate that has an input of an output of an arbitrary flip-flop constituting a first shift register and an output of an arbitrary flip-flop constituting the second shift register; A part of the phase error signal is obtained by using an output signal of a second exclusive OR gate to which an output of an arbitrary flip-flop constituting the shift register and an output of another flip-flop constituting the shift register are inputted. 2. The method according to claim 1, wherein control is performed to determine whether to pass or block the whole. Of the PLL circuit. 4. The reference signal or the reproduction signal is inputted to a first shift register in which flip-flops are connected in cascade, and the output of the flip-flop constituting the shift register and the reference signal or the reproduction signal are inputted. A toggle flip-flop for generating the phase error signal by the output of the exclusive OR gate to input the phase error signal and outputting a control signal as to whether to pass or block a part or all of the phase error signal. The PLL circuit according to claim 1, wherein: 5. A PLL circuit having a phase comparator for detecting a phase difference between a reference signal having a constant frequency or a reproduction signal whose signal change point is not temporally constant and a compared signal and outputting a phase error signal. And a mask means for controlling whether to pass or block a part or all of the phase error signal based on a signal obtained by dividing the phase error signal.
L circuit. 6. A PLL circuit having a phase comparator for detecting a phase difference between a reference signal having a constant frequency or a reproduction signal whose signal change point is not temporally constant and a signal to be compared and outputting a phase error signal. A PLL circuit for inputting the reference signal or the reproduction signal to the phase comparator via frequency dividing means. 7. The PLL circuit according to claim 1, wherein said reference signal or a part of said reproduction signal is cut off when said PLL circuit is locked, and said reference signal is output when said PLL circuit is not locked. A PLL circuit comprising the mask means for passing a signal or the reproduction signal. 8. The PLL circuit according to claim 1, further comprising: said mask means capable of arbitrarily setting a period during which said phase error output is cut off from an external circuit. 9. A reproduction signal in which a change point of a signal recorded on a recording medium with a time width equal to or longer than a minimum time interval Tmin from the fall to the rise of a pulse signal with respect to the sampling interval T is not constant over time, In a PLL circuit having a phase comparator that detects a phase difference from a signal to be compared and outputs a phase error signal, the phase error signal is converted from (Tmin−0.5 · T) to (Tmin).
A PLL circuit comprising mask means for cutting off at a width of (min-1.5 · T).