JPH1154743A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the performance of a MOS-FET, by forming a high- impurity concentration region of a conductivity type reverse to a shallow diffusion layer formed in the peripheral region of a gate electrode under this shallow diffusion layer selectively, and preventing a high impurity concentration distribution from exerting an influence on other regions. SOLUTION: In a silicon substrate 2 for a gate sidewall spacer composed of a silicon nitride film 22 formed on the side of a gate electrode 10, a shallow diffusion layer 16 is formed, and besides a high-impurity concentration region 18 of a conductivity type reverse to the diffusion layer 16 is formed under this. In an element isolation region 4, a shallow diffusion layer 16 and a high- impurity concentration region 18, a deep diffusion layer 24 of the same conductivity type as the shallow diffusion layer 16 is formed. Accordingly, it becomes possible to reduce a junction capacity generated in the junction between the high-impurity concentration region 18 and the deep diffusion layer 24, since the high-impurity concentration region 18 is formed so as not to lap over at least the whole region of the deep diffusion layer 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device having a MOS transistor and a method of manufacturing the same, and more particularly to a semiconductor device including a MOS transistor having a gate length of 0.5 μm or less and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device such as a MOS transistor having a short channel effect with a gate length of 0.5 μm or less, a shallow diffusion layer is formed in a silicon substrate using a gate electrode as a mask. After a gate sidewall spacer is formed on the sidewall of the gate electrode, a deep diffusion layer is formed using the gate electrode and the gate sidewall spacer as a mask. In order to prevent the depletion layer from extending below the gate electrode, a region having a high impurity concentration is formed below the shallow diffusion layer.

FIG. 17 is a diagram showing the structure of the above-described conventional semiconductor device. This semiconductor device is formed by the following manufacturing method. A silicon oxide film 210 having a thickness of 5 [nm] is formed on a silicon substrate 200 by a thermal oxidation method, and an element isolation region 220 is formed by a selective oxidation method or a buried element isolation method. A gate electrode 230 is formed on the silicon substrate 200, and thereafter,
Impurity ions are implanted to form a shallow diffusion layer 240 and a region 250 under the shallow diffusion layer 240 having a conductivity type opposite to that of the diffusion layer 240 and having a high impurity concentration. Subsequently, a gate side wall spacer 260 is formed on the side wall of the gate electrode 230, and then impurity ions are implanted again to form a deep diffusion layer 270.

[0004]

However, in the above-described manufacturing method, as shown in FIG.
Since the region 70 and the region 250 with a high impurity concentration overlap, the junction capacitance generated at the junction between the bottom of the deep diffusion layer 270 and the region 250 with a high impurity concentration increases. In order to prevent the junction capacitance from increasing, a region 2 having a high impurity concentration is used.
There are restrictions on the formation position of 50 and the level of its impurity concentration. As a result, due to the region 250 having a high impurity concentration,
The effect of suppressing the depletion layer from the deep diffusion layer 270 from extending below the gate electrode 230 cannot be sufficiently exhibited,
This hinders the performance improvement of the fine MOS-FET.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and the impurity concentration distribution in a peripheral region of a gate electrode is:
It is an object of the present invention to provide a semiconductor device capable of improving the performance of a MOS-FET without affecting the impurity concentration distribution in other regions, and a method for manufacturing the same.

[0006]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a gate electrode formed on a semiconductor substrate; and a gate electrode formed in the semiconductor substrate below a peripheral region of the gate electrode. A shallow diffusion layer, a deep diffusion layer formed beside the shallow diffusion layer, and a shallow diffusion layer selectively formed under the shallow diffusion layer. And a high region.

In a semiconductor device according to a second aspect of the present invention, the shallow diffusion layer, the deep diffusion layer, and the region having a higher impurity concentration of a conductivity type opposite to the shallow diffusion layer. It is formed in an element formation region surrounded by an isolation region.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device, only the insulating film existing on the side wall of the gate electrode formed on the semiconductor substrate is removed, and the other portions on the semiconductor substrate and the gate electrode are removed. A step of leaving an insulating film thereon; and a step of implanting an impurity into the semiconductor substrate using the gate electrode and the insulating film as a mask.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a first insulating film on a semiconductor substrate; a step of forming a gate electrode on the first insulating film; Forming a second insulating film on the semiconductor substrate including the gate electrode, depositing a third insulating film on a surface other than the convex corners of the second insulating film having irregularities; Removing a part of the second insulating film under etching conditions in which the etching rate of the second insulating film is higher than the etching rate of the third insulating film; and removing the part of the second insulating film. Implanting an impurity into the semiconductor substrate described above.

The method of manufacturing a semiconductor device according to claim 5, wherein a step of forming a first insulating film on the semiconductor substrate; a step of forming a gate electrode on the first insulating film; Forming a second insulating film on the semiconductor substrate including the gate electrode, forming a third insulating film on the second insulating film other than the side wall of the gate electrode, Removing the second insulating film formed on the side wall of the gate electrode using the insulating film as a mask, and implanting impurities into the semiconductor substrate after removing the second insulating film. And characterized in that:

The method of manufacturing a semiconductor device according to claim 6, further comprising the steps of: forming a first insulating film on the semiconductor substrate; forming a gate electrode on the first insulating film; Forming a second insulating film on the semiconductor substrate including the gate electrode, forming a third insulating film on the second insulating film other than the side wall of the gate electrode, Removing the second insulating film formed on the side wall of the gate electrode using the insulating film as a mask, and implanting a first impurity into the semiconductor substrate using the third insulating film as a mask Removing the second and third insulating films, forming a fourth insulating film on the semiconductor substrate including the gate electrode, and performing anisotropic etching on the fourth insulating film. Leaving a fourth insulating film only on the side wall of the gate electrode; And to the gate electrode and the mask the fourth insulating film and the first impurity to the semiconductor substrate, characterized by comprising the step of injecting a second impurity of the opposite conductivity type.

According to a seventh aspect of the present invention, in addition to the structure of the sixth aspect, the method of manufacturing a semiconductor device further comprises a third impurity having a conductivity type opposite to that of the first impurity in a self-aligned manner with the gate electrode.
The method further comprises the step of implanting the impurity at a shallower depth than the first and second impurities.

Further, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a first insulating film on a semiconductor substrate; a step of forming a gate electrode on the first insulating film; Forming a second insulating film on the semiconductor substrate including the gate electrode, anisotropically etching the second insulating film to leave the second insulating film only on the side wall of the gate electrode; Depositing a third insulating film on a surface other than the second insulating film existing on the side wall of the gate electrode; and etching the third insulating film at an etching rate of the third insulating film. Under etching conditions faster than the speed,
A step of removing a part of the second insulating film; and a step of implanting an impurity into the semiconductor substrate from which the part of the second insulating film is removed.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate; forming a gate electrode on the first insulating film; Forming a second insulating film on the semiconductor substrate including the gate electrode, anisotropically etching the second insulating film to leave the second insulating film only on the side wall of the gate electrode; Depositing a third insulating film on a surface other than the second insulating film existing on the side wall of the gate electrode; and forming a third insulating film on the side wall of the gate electrode using the third insulating film as a mask. A step of removing the second insulating film, and a step of implanting impurities into the semiconductor substrate after the step of removing the second insulating film.

Further, according to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first insulating film on a semiconductor substrate; forming a gate electrode on the first insulating film; Forming a second insulating film on the semiconductor substrate including the gate electrode, anisotropically etching the second insulating film to leave the second insulating film only on the side wall of the gate electrode; Implanting a first impurity into the semiconductor substrate using the gate electrode and the second insulating film as a mask; and forming a second impurity existing on a side wall of the gate electrode.
Depositing a third insulating film on a surface other than the insulating film;
Removing the second insulating film present on the side wall of the gate electrode using the third insulating film as a mask, and removing the first insulating film on the semiconductor substrate using the third insulating film as a mask.
Implanting a second impurity of a conductivity type opposite to that of the second impurity.

In the method of manufacturing a semiconductor device according to an eleventh aspect, in addition to the structure of the tenth aspect, a third impurity having a conductivity type opposite to that of the second impurity in a self-aligned manner with the gate electrode. Is implanted shallower than the first and second impurities.

According to a twelfth aspect of the present invention, in the method for manufacturing a semiconductor device according to any one of the third, fourth, fifth, eighth, and ninth aspects, the step of implanting the impurity comprises: Implanting a first impurity ion to form a region having a high impurity concentration, and implanting a second impurity ion having a conductivity type opposite to that of the first impurity ion into the semiconductor substrate to thereby form the region having a high impurity concentration; Forming a shallow diffusion layer over the region.

[0018]

Embodiments of the present invention will be described below with reference to the drawings. First, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described.

FIGS. 1 (a) and 1 (b) to 4 (a) and 4 (b)
FIGS. 4A to 4C are cross-sectional views of respective manufacturing steps showing a method for manufacturing the semiconductor device of the first embodiment. As shown in FIG. 1A, an element isolation region 4 is formed on a silicon substrate 2 by a selective oxidation method or a buried element isolation method. A silicon oxide film 6 of, for example, 4 nm is formed by a thermal oxidation method in which the silicon substrate 2 on which the element isolation regions 4 are formed is thermally oxidized in an atmosphere containing oxygen.

Subsequently, polycrystalline silicon 8 is deposited on the silicon oxide film 6 by chemical vapor deposition (CVD).
After depositing 00 [nm], phosphorus (P), arsenic (As),
Impurities such as boron (B) are ion-implanted into the polycrystalline silicon 8. After that, annealing is performed to activate the impurities. The structure of the semiconductor device that has gone through the steps up to here
This is shown in FIG. Here, by ion implantation,
Although the polycrystalline silicon 8 containing impurities is formed, it may be formed by a method other than ion implantation, for example, a method of directly depositing polycrystalline silicon containing impurities. Polycrystalline silicon containing impurities can be deposited by mixing a gas containing impurities into a source gas by a chemical vapor deposition method (CVD method).

Subsequently, in order to form a gate electrode, the photoresist is patterned using a photolithography method so that the photoresist remains at a place where the gate electrode is to be formed. Using the patterned photoresist as an etching mask, as shown in FIG.
Polycrystalline silicon 8 is anisotropically etched by reactive ion etching to form gate electrode 10. Thereafter, the photoresist is stripped.

Next, a 100 [n] silicon nitride film 12 is formed on the entire surface of the silicon substrate 2 by chemical vapor deposition (CVD).
m] After the deposition, the deposition by chemical vapor deposition (CVD) and the physical etching by argon (Ar) sputtering or the like are performed at the same time, so that the silicon nitride film 12 has Oxide film 1
4 is deposited to form a structure as shown in FIG.

Then, using the silicon oxide film 14 as an etching mask, the silicon nitride film 12 is anisotropically etched by a reactive ion etching method as shown in FIG. Only the silicon nitride film 12 existing in (peripheral portion) is removed.

Next, impurities such as phosphorus, arsenic, boron, indium (In), and antimony (Sb) are ion-implanted into the silicon substrate 2 having the structure shown in FIG.
As shown in FIG. 3A, a shallow diffusion layer 16 and a region 18 having a high impurity concentration of a conductivity type opposite to that of the diffusion layer 16 are formed therebelow.

Subsequently, after the silicon oxide film 14 and the silicon nitride film 12 used as masks for ion implantation are peeled off, as shown in FIG. 3B, a silicon nitride film 20 is formed by chemical vapor deposition (CVD). ) To deposit 100 [nm]. Thereafter, the entire surface of the silicon substrate 2 on which the silicon nitride film 20 is formed is anisotropically etched by a reactive ion etching method, that is, only the silicon nitride film 20 formed on a surface parallel to the surface of the silicon substrate 2 is removed by etching. As shown in FIG. 4A, the silicon nitride film 22 is left only on the side wall of the gate electrode 10.

Further, on the silicon substrate 2 having the structure shown in FIG. 4A, phosphorus, arsenic, boron, indium (I
n), impurities such as antimony (Sb) are ion-implanted to form a shallow diffusion layer 16 and a deep diffusion layer 24 (impurity distribution) of the same conductivity type as shown in FIG.

That is, the semiconductor device manufactured by the manufacturing method of the first embodiment has the following structure. As shown in FIG. 4B, the silicon substrate 2
Is formed with an element isolation region 4, and a silicon oxide film 6 is formed on the surface thereof. A gate electrode 10 is formed on the silicon oxide film 6 in the device forming region between the device isolation regions 4.
Is formed, and a gate sidewall spacer made of a silicon nitride film 22 is formed on the sidewall of the gate electrode 10.

A shallow diffusion layer 16 is formed in the silicon substrate 2 below the gate side wall spacer, and a region 18 having a higher impurity concentration of a conductivity type opposite to that of the diffusion layer 16 is formed below the shallow diffusion layer 16. A deep diffusion layer 24 of the same conductivity type as the shallow diffusion layer 16 is formed between the shallow diffusion layer 16 and the region 18 having a high impurity concentration and the element isolation region 4.

As described above, according to the semiconductor device of the first embodiment, the region 18 having a high impurity concentration is
Since at least the entire region of the deep diffusion layer 24 is formed so as not to overlap, the region 18 having a high impurity concentration and
The junction capacitance generated at the junction with the deep diffusion layer 24 can be reduced.

In the first embodiment, the silicon oxide film 6 formed by thermally oxidizing the silicon substrate 2 in an atmosphere containing oxygen is used. However, the present invention is not limited to this.
Instead of using the silicon oxide film 6, a silicon nitride film thermally nitrided in an atmosphere containing nitrogen, a silicon oxide film and a silicon film deposited by a chemical vapor deposition method, and other films may be used. Thus, the same effect as described above can be obtained.

According to the method of manufacturing the semiconductor device of the first embodiment, the following effects can be obtained at a low manufacturing cost by forming the silicon oxide film 6 by the most commonly used method. realizable. That is, impurities can be implanted only in the peripheral region of the gate electrode,
The impurity concentration distribution in the peripheral region of the gate electrode and the impurity concentration distribution in other regions can be independently formed.
Further, when impurities are implanted into a region other than the periphery of the gate electrode and the semiconductor device is completed while leaving the mask layer formed only on the side wall of the gate electrode, this is the most efficient manufacturing method.

According to the method of manufacturing the semiconductor device of the first embodiment, the gate insulating film contains the nitrogen element, so that it is contained in the polycrystalline silicon 8 in addition to the above effects. It is possible to prevent impurities from diffusing into the silicon substrate.

According to the method of manufacturing a semiconductor device according to the first embodiment, a gate insulating film of a desired material can be deposited by a chemical vapor deposition (CVD) method. A film having a higher dielectric constant than the film can be used as the gate insulating film. Further, interface stress and interface level between the silicon substrate and the gate insulating film can be reduced.

Further, as a material of the gate electrode 10, amorphous silicon is used in place of the polycrystalline silicon 8, or a polycide type laminated structure in which polycrystalline silicon is formed in a lower layer and a silicide film such as tungsten silicide is formed in an upper layer. The same effect as described above can be obtained also when a polymetal type laminated structure in which a metal film such as tungsten is formed on the upper layer with polycrystalline silicon is used.

That is, according to the method of manufacturing the semiconductor device of the first embodiment, by using a conductive material containing silicon as the gate electrode, the type and concentration of the impurities are adjusted to make the gate electrode a desired one. Since the electric property can be adjusted, the performance of the MOS-FET can be easily improved. Further, the impurity can be implanted only in the peripheral region of the gate electrode, and the impurity concentration distribution in the peripheral region of the gate electrode and the impurity concentration distribution in other regions can be independently formed. Further, when impurities are implanted into a region other than the periphery of the gate electrode and the semiconductor device is completed while leaving the mask layer formed only on the side wall of the gate electrode, this is the most efficient manufacturing method.

Further, if the gate electrode is formed of a conductive material containing silicon and a silicide formed thereon, it is possible to reduce the area resistance of the gate electrode. Further, when the gate electrode is made of a conductive material containing silicon and a metal formed thereon, it is possible to further reduce the area resistance of the gate electrode.

In the first embodiment, the silicon oxide film 14 is deposited after the silicon nitride film 12 is deposited. However, the order of the deposition is reversed, and the silicon nitride film is deposited. It may be deposited. In this case, after depositing a silicon oxide film on the entire surface of the silicon substrate 2, the deposition is further performed by a chemical vapor deposition method (CVD method).
By simultaneously performing physical etching by argon (Ar) sputtering or the like, a silicon nitride film is deposited on portions of the silicon oxide film other than the convex corners. Thereafter, using the silicon nitride film as an etching mask, the silicon oxide film is anisotropically etched by a reactive ion etching method to remove only the silicon oxide film present on the side wall (peripheral portion) of the gate electrode 10. .

Next, a method of manufacturing a semiconductor device according to a second embodiment of the present invention will be described. FIG. 5 (a),
FIGS. 8B to 8A and 8B are cross-sectional views of respective manufacturing steps showing a method for manufacturing a semiconductor device according to the second embodiment.

The steps from the formation of the element isolation region to the formation of the gate electrode are the same as in the first embodiment. FIG.
As shown in (a), the element isolation region 3 is formed on the silicon substrate 32 by a selective oxidation method or a buried element isolation method.
4 is formed. A silicon oxide film 36 of, for example, 4 nm is formed by a thermal oxidation method for thermally oxidizing the silicon substrate 32 on which the element isolation regions 34 are formed in an atmosphere containing oxygen.

Subsequently, on the silicon oxide film 36,
Polycrystalline silicon 38 by chemical vapor deposition (CVD)
After depositing 300 [nm], phosphorus (P), arsenic (A)
s) and impurities such as boron (B) are ion-implanted into the polycrystalline silicon. After that, annealing is performed to activate the impurities. FIG. 5A shows the structure of the semiconductor device after the steps up to here. Here, similarly to the first embodiment, the impurity-containing polycrystalline silicon 38 is formed by ion implantation here. However, a method other than ion implantation, for example, a method of directly depositing the impurity-containing polycrystalline silicon is used. It may be formed by. Polycrystalline silicon containing impurities can be deposited by mixing a gas containing impurities into a source gas by a chemical vapor deposition method (CVD method).

Subsequently, in order to form a gate electrode, the photoresist is patterned using a photolithography method so that the photoresist remains at a position where the gate electrode is to be formed. Using the patterned photoresist as an etching mask, as shown in FIG.
Polycrystalline silicon 38 is anisotropically etched by reactive ion etching to form gate electrode 40. Thereafter, the photoresist is stripped.

Next, as shown in FIG. 6A, a silicon nitride film 42 is deposited on the entire surface of the silicon substrate 32 by chemical vapor deposition (CVD) to a thickness of 100 nm. Thereafter, the entire surface of the silicon substrate 32 on which the silicon nitride film 42 is formed is anisotropically etched by a reactive ion etching method, that is, only the silicon nitride film 42 formed on the surface parallel to the silicon substrate 32 is removed by etching. And FIG.
As shown in (b), the silicon nitride film 44 is left only on the side wall of the gate electrode 40.

Subsequently, on the silicon substrate 32 having the structure shown in FIG. 6B, phosphorus, arsenic, boron, indium (I
n) and impurities such as antimony (Sb) are ion-implanted to form a deep diffusion layer 46 (impurity distribution) as shown in FIG.

Next, the silicon oxide film 48 is deposited at portions other than the corners of the projections by simultaneously performing the deposition by the chemical vapor deposition method (CVD method) and the physical etching by argon (Ar) sputtering or the like. Then, a structure as shown in FIG. 7B is formed.

Subsequently, using the silicon oxide film 48 as an etching mask, the silicon nitride film 44 is anisotropically etched by a reactive ion etching method as shown in FIG. Only the silicon nitride film 44 existing in the (peripheral portion) is removed.

Next, on the silicon substrate 32 having the structure shown in FIG. 8A, phosphorus, arsenic, boron, indium (In),
An impurity such as antimony (Sb) is ion-implanted, and FIG.
As shown in FIG. 3B, a shallow diffusion layer 50 of the same conductivity type as the deep diffusion layer 46 and a region 52 having a high impurity concentration of the opposite conductivity type to the diffusion layer 50 are formed therebelow.

That is, the semiconductor device manufactured by the manufacturing method of the second embodiment has the following structure. As shown in FIG. 8B, the silicon substrate 3
2, an element isolation region 34 is formed, and a silicon oxide film 36 is formed on the surface thereof. The element isolation region 3
The gate electrode 40 is formed on the silicon oxide film 36 in the element formation region between the gate electrodes 4 and the silicon oxide film 48 is formed on the gate electrode 40 and the silicon oxide film 36 excluding the side walls of the gate electrode 40. Have been.

In the silicon substrate 32 below the side wall of the gate electrode 40, a shallow diffusion layer 50 is formed, and further below the diffusion layer 50, a region 5 having a reverse conductivity type and a high impurity concentration is formed.
2 are formed. A deep diffusion layer 46 of the same conductivity type as the shallow diffusion layer 50 is formed between the shallow diffusion layer 50 and the region 52 having a high impurity concentration and the element isolation region 34.

As described above, according to the semiconductor device of the second embodiment, the shallow diffusion layer 50 and the region 52 of the opposite conductivity type and high impurity concentration to the diffusion layer 50 have at least the deep diffusion layer 46. Is formed so as not to overlap with the entire region, the junction capacitance generated at the junction between the region 52 having a high impurity concentration and the deep diffusion layer 46 can be reduced.

As in the first embodiment, in the second embodiment, the silicon oxide film 36 is formed by thermally oxidizing the silicon substrate 32 in an atmosphere containing oxygen.
However, the present invention is not limited to this. Instead of the silicon oxide film 36, a silicon nitride film thermally nitrided in an atmosphere containing nitrogen, or a silicon oxide film and a silicon nitride film deposited by a chemical vapor deposition method Further, even when a film other than these is used, the same effect as described above can be obtained.

Further, as a material of the gate electrode 40, amorphous silicon is used in place of the polycrystalline silicon 38, or a polycide type laminated structure in which a polycrystalline silicon is formed in a lower layer and a silicide film such as tungsten silicide is formed in an upper layer. The same effect as described above can be obtained also when a polymetal type laminated structure in which a metal film such as tungsten is formed on the upper layer with polycrystalline silicon is used.

In the second embodiment, after the silicon nitride film 44 is left on the side wall of the gate electrode, the silicon oxide film 48 is deposited on the portion other than the corners of the convex portion. After the silicon oxide film is left on the side wall of the gate electrode, the silicon nitride film may be deposited. In this case, the silicon oxide film is left only on the side wall of the gate electrode 40 by performing anisotropic etching by a reactive ion etching method. Thereafter, a silicon nitride film may be deposited on portions other than the corners of the convex portion, and anisotropically etched by a reactive ion etching method to remove only the silicon oxide film on the side wall of the gate electrode.

Next, a method of manufacturing a semiconductor device according to a modification of the first embodiment will be described. FIG. 9 (a),
12B to 12A and 12B are cross-sectional views of respective manufacturing steps showing a method of manufacturing a semiconductor device according to a modification of the first embodiment.

As shown in FIG. 9A, a silicon substrate 62 is formed by a selective oxidation method or a buried element isolation method.
An element isolation region 64 is formed. A silicon oxide film 66 of, for example, 4 nm is formed by a thermal oxidation method of thermally oxidizing the silicon substrate 62 on which the element isolation regions 64 are formed in an atmosphere containing oxygen.

Subsequently, on the silicon oxide film 66,
Polycrystalline silicon 68 by chemical vapor deposition (CVD)
After depositing 300 [nm], phosphorus (P), arsenic (A)
s) and impurities such as boron (B) are ion-implanted into the polycrystalline silicon 68. After that, annealing is performed to activate the impurities. FIG. 9A shows the structure of the semiconductor device after the above steps. Here, polycrystalline silicon 68 containing impurities is formed by ion implantation, but it may be formed by a method other than ion implantation, for example, a method of directly depositing polycrystalline silicon containing impurities. Polycrystalline silicon containing impurities can be deposited by mixing a gas containing impurities into a source gas by a chemical vapor deposition method (CVD method).

Subsequently, in order to form a gate electrode, the photoresist is patterned by using a photolithography method so that the photoresist remains at a place where the gate electrode is to be formed. Using the patterned photoresist as an etching mask, as shown in FIG.
Polycrystalline silicon 68 and silicon oxide film 66 are anisotropically etched by reactive ion etching to form gate electrode 70. Thereafter, the photoresist is stripped.

Next, a silicon nitride film 72 is formed on the entire surface of the silicon substrate 62 by a chemical vapor deposition method (CVD method).
[Nm], and then further deposited by chemical vapor deposition (CVD).
Method) and physical etching by argon (Ar) sputtering or the like are performed at the same time to deposit a silicon oxide film 74 on portions other than the convex corners of the silicon nitride film 72, as shown in FIG. The structure as shown is formed.

Subsequently, using the silicon oxide film 74 as an etching mask, the silicon nitride film 72 is anisotropically etched by a reactive ion etching method as shown in FIG. Only the silicon nitride film 72 existing in the (peripheral portion) is removed.

Next, on the silicon substrate 62 having the structure shown in FIG. 10B, phosphorus, arsenic, boron, indium (I
n), impurities such as antimony (Sb) are ion-implanted (pocket implantation), and as shown in FIG.
A region 78 of a conductivity type opposite to that of a diffusion layer 76 described later and having a high impurity concentration is formed.

Subsequently, after the silicon oxide film 74 and the silicon nitride film 72 used as masks for ion implantation are separated, impurities such as phosphorus, arsenic, boron, indium (In), and antimony (Sb) are ion-implanted. FIG.
As shown in (b), a shallow diffusion layer 7 is formed over the entire element formation region.
6 is formed.

Subsequently, a silicon nitride film is deposited to a thickness of 100 nm by a chemical vapor deposition (CVD) method. And
The entire surface of the silicon substrate 72 on which the silicon nitride film is formed is anisotropically etched by a reactive ion etching method, that is, only the silicon nitride film formed on a surface parallel to the surface of the silicon substrate 72 is removed by etching.
As shown in (a), the silicon nitride film 82 is left only on the side wall of the gate electrode 70.

Further, impurities such as phosphorus, arsenic, boron, indium (In) and antimony (Sb) are ion-implanted into the silicon substrate 72 having the structure shown in FIG. As shown, a shallow diffusion layer 76 and a deep diffusion layer 84 (impurity distribution) of the same conductivity type are formed.

That is, the semiconductor device manufactured by the manufacturing method of this modified example has the following structure. As shown in FIG. 12B, an element isolation region 64 is formed on the silicon substrate 62, and a gate electrode 70 is formed on the silicon oxide film 66 in the element formation region between the element isolation regions 64. A gate side wall spacer made of a silicon nitride film 82 is formed on the side wall of the gate electrode 70.

In the silicon substrate 62 between the gate electrode 70 and the element isolation region 64, a shallow diffusion layer 76 is formed.
4, a shallow diffusion layer 76 and a deep diffusion layer 84 of the same conductivity type are formed. Further, in the silicon substrate 62 below the gate side wall spacer, a region 78 of a conductivity type opposite to that of the diffusion layer 76 and having a high impurity concentration is formed.

As described above, according to the modification of the first embodiment, the region 78 having a high impurity concentration is formed so as not to overlap at least the entire region of the deep diffusion layer 84. The junction capacitance generated at the junction between the region 78 having a high impurity concentration and the deep diffusion layer 84 can be reduced.

In the above modification, the silicon substrate 62
A silicon oxide film 66 formed by thermally oxidizing a silicon nitride film in an atmosphere containing oxygen is used, but the present invention is not limited to this. A silicon nitride film thermally nitrided in an atmosphere containing nitrogen instead of this silicon oxide film is used. Alternatively, the same effects as described above can be obtained also when a silicon oxide film and a silicon film deposited by a chemical vapor deposition method, and a film other than these are used.

Further, as a material of the gate electrode 70, an amorphous silicon is used instead of the polycrystalline silicon 68, a polycide type laminated structure in which a polycrystalline silicon is formed in a lower layer and a silicide film such as tungsten silicide is formed in an upper layer, The same effect as described above can be obtained even when a polymetal type laminated structure in which a metal film such as tungsten is formed in the lower layer and polycrystalline silicon is formed in the lower layer.

Next, a method for manufacturing a semiconductor device according to a modification of the second embodiment will be described. FIG. 13 (a),
FIGS. 16B to 16A and 16B are cross-sectional views of respective manufacturing steps showing a method of manufacturing a semiconductor device according to a modification of the second embodiment.

As shown in FIG. 13A, a silicon substrate 9 is formed by a selective oxidation method or a buried element isolation method.
2, an element isolation region 94 is formed. A silicon oxide film 96 of, for example, 4 nm is formed by a thermal oxidation method of thermally oxidizing the silicon substrate 92 on which the element isolation regions 94 are formed in an atmosphere containing oxygen.

Subsequently, on the silicon oxide film 96,
Polycrystalline silicon 98 by chemical vapor deposition (CVD)
After depositing 300 [nm], phosphorus (P), arsenic (A)
s) and impurities such as boron (B) are ion-implanted into the polycrystalline silicon 98. After that, annealing is performed to activate the impurities. FIG. 13A shows the structure of the semiconductor device after the steps up to here. Here, similarly to the first embodiment, the impurity-containing polycrystalline silicon 98 is formed by ion implantation here. However, a method other than ion implantation, for example, a method of directly depositing the impurity-containing polycrystalline silicon is used. It may be formed by. The polycrystalline silicon containing the impurities is formed by a chemical vapor deposition (CVD) method.
Accordingly, deposition can be performed by mixing a gas containing impurities into the source gas.

Subsequently, in order to form a gate electrode, the photoresist is patterned using a photolithography method so that the photoresist remains at a place where the gate electrode is to be formed. Using the patterned photoresist as an etching mask, as shown in FIG.
8 is anisotropically etched to form a gate electrode 100. In addition, phosphorus, arsenic, boron, indium (I
n), an impurity such as antimony (Sb) is ion-implanted to form a shallow diffusion layer 102 over the entire element formation region.

Next, as shown in FIG. 14A, a silicon nitride film 104 is deposited on the entire surface of the silicon substrate 92 by a chemical vapor deposition method (CVD method) to a thickness of 100 nm. Thereafter, the entire surface of the silicon substrate 92 on which the silicon nitride film 104 is formed is anisotropically etched by a reactive ion etching method, that is, only the silicon nitride film 104 formed on a surface parallel to the surface of the silicon substrate 92 is removed by etching. Then, as shown in FIG. 14B, the silicon nitride film 106 is left only on the side wall of the gate electrode 100.

Subsequently, phosphorus, arsenic, boron and indium (I) were deposited on the silicon substrate 92 having the structure shown in FIG.
n), impurities such as antimony (Sb) are ion-implanted to form a deep diffusion layer 108 (impurity distribution) as shown in FIG.

Next, the silicon oxide film 110 is deposited on portions other than the corners of the projections by simultaneously performing deposition by a chemical vapor deposition method (CVD method) and physical etching by argon (Ar) sputtering or the like. , FIG.
A structure as shown in FIG.

Then, using the silicon oxide film 110 as an etching mask, the silicon nitride film 106 is anisotropically etched by a reactive ion etching method as shown in FIG. Only the silicon nitride film 106 existing in the (peripheral portion) is removed.

Next, phosphorus, arsenic, boron, indium (I) is deposited on the silicon substrate 92 having the structure shown in FIG.
n), impurities such as antimony (Sb) are ion-implanted (pocket implantation), and as shown in FIG.
A region 112 having a high impurity concentration of the opposite conductivity type to the shallow diffusion layer 102 is formed.

That is, the semiconductor device manufactured according to this modification has the following structure. FIG.
As shown in FIG. 2B, an element isolation region 94 is formed in the silicon substrate 92, a gate electrode 100 is formed on the silicon oxide film 96 in an element formation region between the element isolation regions 94, and further, the gate electrode 100 is formed. A silicon oxide film 11 is formed on the electrode 100 and on a region other than the side wall of the gate electrode 100.
0 is formed.

The gate electrode 100 and the element isolation region 94
A shallow diffusion layer 102 is formed in a silicon substrate 92 between the gate electrode 100 and the element isolation region 94.
A deep diffusion layer 108 of the same conductivity type as the shallow diffusion layer 102 is formed in the silicon substrate 92 except for the peripheral portion of the side wall of the gate electrode 100 between the gate electrode 100 and the gate electrode 100. Further, in the silicon substrate 92 below the peripheral portion of the side wall of the gate electrode 100, a region 112 having a high impurity concentration of a conductivity type opposite to that of the shallow diffusion layer 102 is formed.

As described above, according to the modification of the second embodiment, the shallow diffusion layer 102 and the diffusion layer 1
02 is formed so as not to overlap with at least the entire region of the deep diffusion layer 108, so that the region 112 having a high impurity concentration is formed so as not to overlap with at least the entire region of the deep diffusion layer 108.
Thus, the junction capacitance generated at the junction with the deep diffusion layer 108 can be reduced.

In the above modification, the silicon substrate 92
Silicon oxide film 96 formed by thermal oxidation in an atmosphere containing oxygen is used, but the present invention is not limited to this. A silicon nitride film thermally nitrided in an atmosphere containing nitrogen instead of this silicon oxide film is used. Alternatively, the same effects as described above can be obtained also when a silicon oxide film and a silicon film deposited by a chemical vapor deposition method, and a film other than these are used.

Further, as a material of the gate electrode 100,
Instead of the polycrystalline silicon 98, an amorphous silicon is used, a polycide type laminated structure in which a polycrystalline silicon is formed in a lower layer, a silicide film such as tungsten silicide is formed in an upper layer, and a polycrystalline silicon is formed in a lower layer and a metal such as tungsten is formed in an upper layer. The same effects as described above can be obtained also when a polymetal-type laminated structure having a film is used.

As described above, in the above-described embodiment, pocket implantation can be performed only around the gate electrode in order to increase the flexibility of pocket implantation. As a result, restrictions on the depth of the peak of the pocket implant and the impurity concentration to be implanted can be reduced, and the performance of the fine MOS-FET can be improved.

The semiconductor device of the first embodiment shown in FIGS. 1 to 4 and the semiconductor device of the second embodiment shown in FIGS. Is more advantageous in reducing the number of steps since a shallow diffusion layer and a region with high impurity concentration (pocket implantation) can be formed using the same mask.

[0084]

As described above, according to the present invention, the impurity can be implanted only in the peripheral region of the gate electrode, and the impurity concentration distribution in the peripheral region of the gate electrode can be reduced. It is possible to provide a semiconductor device capable of improving the performance of a MOS-FET without affecting the impurity concentration distribution, and a method for manufacturing the same.

According to the semiconductor device of the first and second aspects of the present invention, the impurity concentration distribution in the peripheral region of the gate electrode and the impurity concentration distribution in the other region are independently formed. The impurity concentration distribution in the peripheral region of the gate electrode does not affect the impurity concentration distribution in other regions, and the performance of the MOS-FET can be improved.

According to the method of manufacturing a semiconductor device according to the third aspect of the present invention, the impurity can be implanted only in the peripheral region of the gate electrode. And the impurity concentration distribution in the other regions can be made independently.

According to the method of manufacturing a semiconductor device of the present invention, the impurity can be implanted only in the peripheral region of the gate electrode.
The impurity concentration distribution in the peripheral region of the gate electrode and the impurity concentration distribution in other regions can be independently formed.
Furthermore, when impurity ions are implanted into a region other than the periphery of the gate electrode, the most efficient manufacturing method is used when a semiconductor device is completed while leaving the mask layer formed only on the side wall of the gate electrode.

According to the method of manufacturing a semiconductor device of the present invention, the impurity can be implanted only in the peripheral region of the gate electrode. And the impurity concentration distribution in the other region can be made independently. Further, when impurity ions are implanted into a region other than the periphery of the gate electrode, the mask layer formed only on the side wall of the gate electrode is removed, and then the semiconductor device is completed. .

According to the method of manufacturing a semiconductor device according to the twelfth aspect of the present invention, the impurity ions can be implanted only in the peripheral region of the gate electrode. The impurity concentration distribution in the impurity region and the impurity concentration distribution in other regions can be independently formed.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device according to a first embodiment.

FIG. 2 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the first embodiment.

FIG. 3 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the first embodiment.

FIG. 4 is a cross-sectional view of each manufacturing step showing the semiconductor device of the first embodiment and a method of manufacturing the same.

FIG. 5 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the second embodiment.

FIG. 6 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the second embodiment.

FIG. 7 is a cross-sectional view of each manufacturing step showing the method for manufacturing a semiconductor device of the second embodiment.

FIG. 8 is a cross-sectional view of each manufacturing step showing the semiconductor device of the second embodiment and a method of manufacturing the same.

FIG. 9 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device according to a modification of the first embodiment.

FIG. 10 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device according to a modification of the first embodiment.

FIG. 11 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device according to a modified example of the first embodiment.

FIG. 12 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device according to a modified example of the first embodiment.

FIG. 13 is a cross-sectional view of each manufacturing step showing a method of manufacturing a semiconductor device according to a modification of the second embodiment.

FIG. 14 is a cross-sectional view of each manufacturing step showing a method of manufacturing a semiconductor device according to a modification of the second embodiment.

FIG. 15 is a cross-sectional view of each manufacturing step showing a method of manufacturing a semiconductor device according to a modification of the second embodiment.

FIG. 16 is a cross-sectional view of each manufacturing step showing a method for manufacturing a semiconductor device according to a modification of the second embodiment.

FIG. 17 is a diagram illustrating a structure of a conventional semiconductor device.

[Explanation of symbols]

2, 32, 62, 92: silicon substrate 4, 34, 64, 94: element isolation region 6, 14, 36, 48, 66, 74, 96: silicon oxide film 8, 38, 68, 98: polycrystalline silicon 10 , 40, 70, 100 ... gate electrodes 12, 20, 22, 42, 44, 72, 82, 104,
106, 110: Silicon nitride film 16, 50, 76, 102: Shallow diffusion layer 18, 52, 78, 112: High impurity concentration region 24, 46, 84, 108: Deep diffusion layer

Claims (12)

[Claims] 1. A gate electrode formed on a semiconductor substrate, a shallow diffusion layer formed in the semiconductor substrate below a peripheral region of the gate electrode, and a deep diffusion layer formed beside the shallow diffusion layer A semiconductor device selectively formed under the shallow diffusion layer and having a region with a high impurity concentration of an opposite conductivity type to the shallow diffusion layer. 2. The device according to claim 1, wherein the shallow diffusion layer, the deep diffusion layer, and a region having a high impurity concentration of a conductivity type opposite to that of the shallow diffusion layer are formed in an element formation region surrounded by an element isolation region. 2. The semiconductor device according to claim 1, wherein: 3. A step of removing only an insulating film existing on a side wall of a gate electrode formed on a semiconductor substrate, and leaving an insulating film on the other semiconductor substrate and the gate electrode; And a step of injecting impurities into the semiconductor substrate using the insulating film as a mask. 4. A step of forming a first insulating film on a semiconductor substrate, a step of forming a gate electrode on the first insulating film, and a second insulating film on a semiconductor substrate including the gate electrode Forming a third insulating film on a surface other than the convex corners of the second insulating film having irregularities; and etching the second insulating film at an etching rate of the third insulating film. Removing a portion of the second insulating film under etching conditions faster than the etching rate of the film; implanting an impurity into the semiconductor substrate from which a portion of the second insulating film has been removed; A method for manufacturing a semiconductor device, comprising: 5. A step of forming a first insulating film on a semiconductor substrate, a step of forming a gate electrode on the first insulating film, and a second insulating film on a semiconductor substrate including the gate electrode Forming a third insulating film on the second insulating film other than the side wall portion of the gate electrode; and forming a third insulating film on the side wall portion of the gate electrode using the third insulating film as a mask. A step of removing the formed second insulating film; and a step of implanting an impurity into the semiconductor substrate after the step of removing the second insulating film. Production method. 6. A step of forming a first insulating film on a semiconductor substrate, a step of forming a gate electrode on the first insulating film, and a second insulating film on a semiconductor substrate including the gate electrode Forming a third insulating film on the second insulating film other than the side wall portion of the gate electrode; and forming a third insulating film on the side wall portion of the gate electrode using the third insulating film as a mask. Removing the formed second insulating film; and forming the first insulating film on the semiconductor substrate using the third insulating film as a mask.
Implanting impurities, removing the second and third insulating films, forming a fourth insulating film on the semiconductor substrate including the gate electrode, and removing the fourth insulating film. Anisotropically etching to leave a fourth insulating film only on the side wall of the gate electrode; and using the first impurity in the semiconductor substrate using the gate electrode and the fourth insulating film as a mask. Implanting a second impurity of the opposite conductivity type. A method for manufacturing a semiconductor device, comprising: 7. The first electrode in a self-aligned manner with the gate electrode.
The third impurity of the opposite conductivity type to the first and second impurities
7. The method of manufacturing a semiconductor device according to claim 6, further comprising a step of implanting the impurity at a depth smaller than that of the impurity. 8. A step of forming a first insulating film on a semiconductor substrate, a step of forming a gate electrode on the first insulating film, and a second insulating film on a semiconductor substrate including the gate electrode Forming a second insulating film on the side wall of the gate electrode by anisotropically etching the second insulating film; leaving the second insulating film only on the side wall of the gate electrode; Depositing a third insulating film on a surface other than the insulating film, and etching the second insulating film under an etching condition in which the etching rate of the second insulating film is higher than the etching rate of the third insulating film. A method of manufacturing a semiconductor device, comprising: a step of removing a part of a film; and a step of implanting an impurity into the semiconductor substrate from which a part of the second insulating film has been removed. 9. A step of forming a first insulating film on a semiconductor substrate, a step of forming a gate electrode on the first insulating film, and a second insulating film on a semiconductor substrate including the gate electrode Forming a second insulating film on the side wall of the gate electrode by anisotropically etching the second insulating film; leaving the second insulating film only on the side wall of the gate electrode; Depositing a third insulating film on a surface other than the insulating film, and removing the second insulating film present on the side wall of the gate electrode using the third insulating film as a mask; A step of implanting an impurity into the semiconductor substrate after the step of removing the second insulating film. 10. A step of forming a first insulating film on a semiconductor substrate, a step of forming a gate electrode on the first insulating film, and a second insulating film on a semiconductor substrate including the gate electrode Forming a second insulating film, anisotropically etching the second insulating film to leave the second insulating film only on the side wall of the gate electrode, and masking the gate electrode and the second insulating film. Implanting a first impurity into the semiconductor substrate, depositing a third insulating film on a surface other than the second insulating film existing on the side wall of the gate electrode, Removing the second insulating film present on the side wall of the gate electrode using the insulating film as a mask, and removing the second impurity from the first impurity in the semiconductor substrate using the third insulating film as a mask. Implanting a second impurity of conductivity type; The method of manufacturing a semiconductor device according to claim Rukoto. 11. The method according to claim 1, further comprising the step of implanting a third impurity of a conductivity type opposite to that of said second impurity to a depth shallower than said first and second impurities in a self-aligned manner with said gate electrode. The method of manufacturing a semiconductor device according to claim 10. 12. The step of implanting the impurity includes the step of implanting a first impurity ion into the semiconductor substrate to form a region having a high impurity concentration, and the step of implanting a first impurity ion having a conductivity type opposite to that of the first impurity ion. Forming a shallow diffusion layer on the region having a high impurity concentration by implanting the second impurity ions into the semiconductor substrate.
10. The method for manufacturing a semiconductor device according to any one of 5, 8, and 9.