JPH11512571A - 低rc配線 - Google Patents
低rc配線Info
- Publication number
- JPH11512571A JPH11512571A JP9512716A JP51271697A JPH11512571A JP H11512571 A JPH11512571 A JP H11512571A JP 9512716 A JP9512716 A JP 9512716A JP 51271697 A JP51271697 A JP 51271697A JP H11512571 A JPH11512571 A JP H11512571A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- layer
- manufacturing
- metal
- copper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Local Oxidation Of Silicon (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.配線パターンを有する半導体装置であって、 誘電体層と、 金属層と、 金属層と誘電体層との間の中間ボンディング層とを含み、 金属層は中間ボンディング層を介して誘電体層にボンディングされる、半導体 装置。 2.中間層は、付着助触媒と金属との反応生成物を含む、請求項1に記載の半導 体装置。 3.付着助触媒はシランベースの有機物を含む、請求項2に記載の半導体装置。 4.シランベースの有機物は、3−アミノプロピルトリエトキシシランおよび3 −メタクリルオキシプロピルトリメトキシシランからなるグループから選択され る、請求項3に記載の半導体装置。 5.シランベースの有機物は、ビニル、クロロプロピル、エポキシ、ジアミン、 メルカプトおよび/またはカチオンスチリル有機官能基を含む、請求項3に記載 の半導体装置。 6.ボンディング層は、付着助触媒を、金属層の表面および/または誘電体層の 表面に塗布することによって形成される、請求項2に記載の半導体装置。 7.誘電体層は、付着助触媒を含む、請求項2に記載の半導体装置。 8.金属層は、銅、銅ベースの合金、金、金ベースの合金、銀および銀ベースの 合金からなるグループから選択される低抵抗率金属を含む、請求項1に記載の半 導体装置。 9.金属は銅または銅ベースの合金である、請求項8に記載の半導体装置。 10.誘電体層は、約3.5よりも小さい誘電率を有する誘電体材料を含む、請 求項1に記載の半導体装置。 11.誘電体層は、約3.0よりも小さい誘電率を有する誘電体材料を含む、請 求項10に記載の半導体装置。 12.誘電体層は、低誘電率ポリマーを含む、請求項1に記載の半導体装置。 13.低誘電率ポリマーは、ポリイミド、テフロン、BCB、パリレンおよびシ ルセスキオキサンからなるグループから選択される、請求項12に記載の半導体 装置。 14.金属層は、導電パターンを含む、請求項1に記載の半導体装置。 15.配線パターンを有する半導体装置を製造する方法であって、前記方法は、 金属層を中間ボンディング層を介して誘電体層にボンディングするステップを含 む、半導体装置を製造する方法。 16.ボンディングは、中間ボンディング層を形成するよう付着助触媒によって 行なわれる、請求項15に記載の半導体装置を製造する方法。 17.付着助触媒はシランベースの有機物を含む、請求項16に記載の半導体装 置を製造する方法。 18.シランベースの有機物は、3−アミノプロピルトリエトキシシランおよび 3−メタクリルオキシプロピルトリメトキシシランからなるグループから選択さ れる、請求項17に記載の半導体装置を製造する方法。 19.シランベースの有機物は、ビニル、クロロプロピル、エポキシ、ジアミン 、メルカプトおよび/またはカチオンスチリル有機官能基を含む、請求項17に 記載の半導体装置を製造する方法。 20.付着助触媒を金属層の表面および/または誘電体層の表面に塗布するステ ップをさらに含む、請求項16に記載の半導体装置を製造する方法。 21.付着助触媒を誘電体層に組入れるステップをさらに含む、請求項16に記 載の半導体装置を製造する方法。 22.金属層は、銅、銅ベースの合金、金、金ベースの合金、銀および銀ベース の合金からなるグループから選択される低抵抗率金属を含む、請求項15に記載 の半導体装置を製造する方法。 23.金属は、銅または銅ベースの合金である、請求項22に記載の半導体装置 を製造する方法。 24.誘電体層は、約3.5よりも小さい誘電率を有する誘電体材料を含む、請 求項15に記載の半導体装置を製造する方法。 25.誘電率は約3.0よりも小さい、請求項24に記載の半導体装置を製造す る方法。 26.誘電体層は低誘電率ポリマーを含む、請求項15に記載の半導体装置を製 造する方法。 27.低誘電率ポリマーは、ポリイミド、テフロン、BCB、パリレンおよびシ ルセスキオキサンからなるグループから選択される、請求項26に記載の半導体 装置を製造する方法。 28.金属層は、ダマシーンプロセスにより形成される導電パターンを含む、請 求項15に記載の半導体装置を製造する方法。 29.金属層を堆積するステップと、金属パターンを形成するためエッチングす るステップと、その上に誘電体層を堆積するステップとを含む、請求項16に記 載の半導体装置を製造する方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/530,658 | 1995-09-20 | ||
US08/530,658 US5760480A (en) | 1995-09-20 | 1995-09-20 | Low RC interconnection |
PCT/US1996/013935 WO1997011490A1 (en) | 1995-09-20 | 1996-09-18 | Low rc interconnection |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH11512571A true JPH11512571A (ja) | 1999-10-26 |
JP4178272B2 JP4178272B2 (ja) | 2008-11-12 |
Family
ID=24114466
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP51271697A Expired - Fee Related JP4178272B2 (ja) | 1995-09-20 | 1996-09-18 | 半導体装置およびこれを製造する方法 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5760480A (ja) |
EP (2) | EP0852067B1 (ja) |
JP (1) | JP4178272B2 (ja) |
DE (2) | DE69637537D1 (ja) |
WO (1) | WO1997011490A1 (ja) |
Families Citing this family (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6294455B1 (en) | 1997-08-20 | 2001-09-25 | Micron Technology, Inc. | Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry |
US6136682A (en) * | 1997-10-20 | 2000-10-24 | Motorola Inc. | Method for forming a conductive structure having a composite or amorphous barrier layer |
US6870263B1 (en) * | 1998-03-31 | 2005-03-22 | Infineon Technologies Ag | Device interconnection |
US6265780B1 (en) * | 1998-12-01 | 2001-07-24 | United Microelectronics Corp. | Dual damascene structure for the wiring-line structures of multi-level interconnects in integrated circuit |
US6165898A (en) * | 1998-10-23 | 2000-12-26 | Taiwan Semiconductor Manufacturing Company | Dual damascene patterned conductor layer formation method without etch stop layer |
US6291887B1 (en) | 1999-01-04 | 2001-09-18 | Advanced Micro Devices, Inc. | Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer |
US6153514A (en) * | 1999-01-04 | 2000-11-28 | Advanced Micro Devices, Inc. | Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer |
US6255735B1 (en) * | 1999-01-05 | 2001-07-03 | Advanced Micro Devices, Inc. | Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers |
US6207577B1 (en) | 1999-01-27 | 2001-03-27 | Advanced Micro Devices, Inc. | Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer |
US6380091B1 (en) | 1999-01-27 | 2002-04-30 | Advanced Micro Devices, Inc. | Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer |
US6369452B1 (en) * | 1999-07-27 | 2002-04-09 | International Business Machines Corporation | Cap attach surface modification for improved adhesion |
US6414377B1 (en) * | 1999-08-10 | 2002-07-02 | International Business Machines Corporation | Low k dielectric materials with inherent copper ion migration barrier |
US6265319B1 (en) | 1999-09-01 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Dual damascene method employing spin-on polymer (SOP) etch stop layer |
DE19949738A1 (de) * | 1999-10-15 | 2001-05-23 | Karlsruhe Forschzent | Verfahren zur Herstellung von Oberflächenwellensensoren und Oberflächenwellensensor |
US6596623B1 (en) | 2000-03-17 | 2003-07-22 | Advanced Micro Devices, Inc. | Use of organic spin on materials as a stop-layer for local interconnect, contact and via layers |
DE10059935A1 (de) * | 2000-11-28 | 2002-06-06 | Infineon Technologies Ag | Dicht gepackte Halbleiterstruktur und Verfahren zum Herstellen einer solchen |
US6445070B1 (en) * | 2000-12-18 | 2002-09-03 | Advanced Micro Devices, Inc. | Coherent carbide diffusion barrier for integrated circuit interconnects |
US6455443B1 (en) * | 2001-02-21 | 2002-09-24 | International Business Machines Corporation | Method of fabricating low-dielectric constant interlevel dielectric films for BEOL interconnects with enhanced adhesion and low-defect density |
US6724069B2 (en) * | 2001-04-05 | 2004-04-20 | International Business Machines Corporation | Spin-on cap layer, and semiconductor device containing same |
US6974762B2 (en) * | 2002-08-01 | 2005-12-13 | Intel Corporation | Adhesion of carbon doped oxides by silanization |
US7005390B2 (en) * | 2002-10-09 | 2006-02-28 | Intel Corporation | Replenishment of surface carbon and surface passivation of low-k porous silicon-based dielectric materials |
US6858527B2 (en) * | 2003-04-14 | 2005-02-22 | Intel Corporation | Method to increase electromigration resistance of copper using self-assembled organic thiolate monolayers |
US6737313B1 (en) | 2003-04-16 | 2004-05-18 | Micron Technology, Inc. | Surface treatment of an oxide layer to enhance adhesion of a ruthenium metal layer |
DE102004026092A1 (de) * | 2004-05-25 | 2005-12-22 | Infineon Technologies Ag | Verfahren zur Herstellung einer mit einem Moldcompound versehenen Chip-Anordnung |
US10199266B2 (en) | 2016-12-26 | 2019-02-05 | Intel Corporation | Integrated circuit interconnect structure having metal oxide adhesive layer |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4720424A (en) * | 1984-06-18 | 1988-01-19 | Hoebbst Celanese Corporation | Electronic component encapsulated with a composition comprising a polymer which is capable of forming an anisotropic melt phase and substantially incapable of further chain growth upon heating |
DE3630497A1 (de) * | 1986-09-08 | 1988-03-10 | Behringwerke Ag | Cis-platin-komplexe, verfahren zu ihrer herstellung und diese verbindungen enthaltende pharmazeutische mittel |
US5079600A (en) * | 1987-03-06 | 1992-01-07 | Schnur Joel M | High resolution patterning on solid substrates |
US5091251A (en) * | 1989-05-29 | 1992-02-25 | Tomoegawa Paper Co., Ltd. | Adhesive tapes and semiconductor devices |
US5115090A (en) * | 1990-03-30 | 1992-05-19 | Sachdev Krishna G | Viscosity stable, essentially gel-free polyamic acid compositions |
US5114757A (en) * | 1990-10-26 | 1992-05-19 | Linde Harold G | Enhancement of polyimide adhesion on reactive metals |
US5194928A (en) * | 1991-01-14 | 1993-03-16 | International Business Machines Corporation | Passivation of metal in metal/polyimide structure |
US5114754A (en) * | 1991-01-14 | 1992-05-19 | International Business Machines Corporation | Passivation of metal in metal/polyimide structures |
US5196103A (en) * | 1991-07-12 | 1993-03-23 | The Dow Chemical Company | Method of making an electrical interconnection device |
US5153986A (en) * | 1991-07-17 | 1992-10-13 | International Business Machines | Method for fabricating metal core layers for a multi-layer circuit board |
US5397741A (en) * | 1993-03-29 | 1995-03-14 | International Business Machines Corporation | Process for metallized vias in polyimide |
-
1995
- 1995-09-20 US US08/530,658 patent/US5760480A/en not_active Expired - Lifetime
-
1996
- 1996-09-18 JP JP51271697A patent/JP4178272B2/ja not_active Expired - Fee Related
- 1996-09-18 EP EP96929805A patent/EP0852067B1/en not_active Expired - Lifetime
- 1996-09-18 WO PCT/US1996/013935 patent/WO1997011490A1/en active IP Right Grant
- 1996-09-18 DE DE69637537T patent/DE69637537D1/de not_active Expired - Lifetime
- 1996-09-18 EP EP98201222A patent/EP0860880B1/en not_active Expired - Lifetime
- 1996-09-18 DE DE69631963T patent/DE69631963T2/de not_active Expired - Lifetime
-
1997
- 1997-07-10 US US08/890,905 patent/US5861677A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0852067A1 (en) | 1998-07-08 |
DE69637537D1 (de) | 2008-07-03 |
EP0860880A2 (en) | 1998-08-26 |
WO1997011490A1 (en) | 1997-03-27 |
US5861677A (en) | 1999-01-19 |
JP4178272B2 (ja) | 2008-11-12 |
EP0860880B1 (en) | 2008-05-21 |
EP0852067B1 (en) | 2004-03-24 |
DE69631963D1 (de) | 2004-04-29 |
EP0860880A3 (en) | 1999-02-03 |
DE69631963T2 (de) | 2005-04-07 |
US5760480A (en) | 1998-06-02 |
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