JPH11511907A - スタンダードセルライブラリの最適化方法及び装置 - Google Patents

スタンダードセルライブラリの最適化方法及び装置

Info

Publication number
JPH11511907A
JPH11511907A JP10501863A JP50186398A JPH11511907A JP H11511907 A JPH11511907 A JP H11511907A JP 10501863 A JP10501863 A JP 10501863A JP 50186398 A JP50186398 A JP 50186398A JP H11511907 A JPH11511907 A JP H11511907A
Authority
JP
Japan
Prior art keywords
size
library
standard cell
pmos
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP10501863A
Other languages
English (en)
Japanese (ja)
Inventor
フィッシャー，ルイス，シー．
ジェンセン，ジョーン，エス．
ロスマン，トーマス，エフ．
Original Assignee
カスケード デザイン オートメーション コーポレイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by カスケード デザイン オートメーション コーポレイション filed Critical カスケード デザイン オートメーション コーポレイション
Publication of JPH11511907A publication Critical patent/JPH11511907A/ja
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/06—Power analysis or power optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP10501863A 1996-06-14 1997-06-13 スタンダードセルライブラリの最適化方法及び装置 Withdrawn JPH11511907A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US1976796P 1996-06-14 1996-06-14
US60/019,767 1996-06-14
PCT/US1997/010305 WO1997048061A1 (fr) 1996-06-14 1997-06-13 Procede et systeme d'optimisation de bibliotheques de cellules standards

Publications (1)

Publication Number Publication Date
JPH11511907A true JPH11511907A (ja) 1999-10-12

Family

ID=21794930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10501863A Withdrawn JPH11511907A (ja) 1996-06-14 1997-06-13 スタンダードセルライブラリの最適化方法及び装置

Country Status (5)

Country Link
EP (1) EP0852768A1 (fr)
JP (1) JPH11511907A (fr)
AU (1) AU3570697A (fr)
CA (1) CA2229404A1 (fr)
WO (1) WO1997048061A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007052334A1 (fr) * 2005-11-01 2007-05-10 Fujitsu Limited Procédé et programme servant à réaliser la configuration d’une cellule logique

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6124250A (ja) * 1984-07-13 1986-02-01 Nippon Gakki Seizo Kk 半導体集積回路装置
JPS63308343A (ja) * 1987-06-10 1988-12-15 Matsushita Electric Ind Co Ltd 半導体集積回路
US5031111C1 (en) * 1988-08-08 2001-03-27 Trw Inc Automated circuit design method
US5173864A (en) * 1988-08-20 1992-12-22 Kabushiki Kaisha Toshiba Standard cell and standard-cell-type integrated circuit
JP3017789B2 (ja) * 1990-10-18 2000-03-13 三菱電機株式会社 半導体集積回路装置のレイアウト設計方法
US5459673A (en) * 1990-10-29 1995-10-17 Ross Technology, Inc. Method and apparatus for optimizing electronic circuits
US5225991A (en) * 1991-04-11 1993-07-06 International Business Machines Corporation Optimized automated macro embedding for standard cell blocks
JPH05274390A (ja) * 1992-03-30 1993-10-22 Matsushita Electric Ind Co Ltd 回路素子割り付け方法及び遅延最適化方法並びに論理設計システム
US5487018A (en) * 1993-08-13 1996-01-23 Vlsi Technology, Inc. Electronic design automation apparatus and method utilizing a physical information database
US5563801A (en) * 1993-10-06 1996-10-08 Nsoft Systems, Inc. Process independent design for gate array devices

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007052334A1 (fr) * 2005-11-01 2007-05-10 Fujitsu Limited Procédé et programme servant à réaliser la configuration d’une cellule logique
US7913211B2 (en) 2005-11-01 2011-03-22 Fujitsu Limited Logic cell configuration processing method and program

Also Published As

Publication number Publication date
WO1997048061A1 (fr) 1997-12-18
CA2229404A1 (fr) 1997-12-18
AU3570697A (en) 1998-01-07
EP0852768A1 (fr) 1998-07-15

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Legal Events

Date Code Title Description
A761 Written withdrawal of application

Free format text: JAPANESE INTERMEDIATE CODE: A761

Effective date: 20040528